Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

Analysis and Design of a Transmitter for Wireless Communications in CMOS Technology

The number of wireless devices has grown tremendously over the last decade. Great technology improvements and novel transceiver architectures and circuits have enabled an astonishingly expanding set of radio-frequency applications. CMOS technology played a key role in enabling a large-scale diffusion of wireless devices due to its unique advantages in cost and integration. Novel digital-intensive transceivers have taken full advantage of CMOS technology scaling predicted by Moore's law. Die-shrinking has enabled ubiquitous diffusion of low-cost, small form factor and low power wireless devices. However, Radio Frequency (RF) Power Amplifiers (PA) transceiver functionality is historically implemented in a module which is separated from the CMOS core of the transceiver. The PA is traditionally dictating power and battery life of the transceiver, thus justifying its implementation in a tailored technology. By contrast, a fully integrated CMOS transceiver with no external PA would hugely benefit in terms of reduced area and system complexity. In this work, a fully integrated prototype of a Switched-Capacitor Power Amplifier (SCPA) has been implemented in a 28nm CMOS technology. The SCPA provides the functionalities of a PA and of a Radio-Frequency Digital-to-Analog Converter (RF-DAC) in a monolithic CMOS device. The switching output stage of the SCPA enables this circuital topology to reach high efficiencies and offers excellent power handling capabilities. In this work, the properties of the SCPA are analyzed in an extensive and detailed dissertation. Nowadays Wireless Communications operate in a very crowded spectrum, with strict coexistence requirements, thus demanding a strong linearity to the RF-DAC section of the SCPA. A great part of the work of designing a good SCPA is in fact designing a good RF-DAC. To enhance RF-DAC linearity, a precision of the timing of the elements up to the ps range is required. The use of a single core-supply voltage in the whole circuit including the CMOS inverter of the switching output stage enables the use of minimum size devices, improving accuracy and speed in the timing of the elements. The whole circuit operates therefore on low core-supply voltage. Throughout this work, a detailed analysis carefully describes the electromagnetic structures which maximize power and efficiency of low-voltage SCPAs. Due to layout issues subsequent to limited available voltages, however, there is a practical limitation in the maximum achievable power of low-voltage SCPAs. In this work, a Multi-Port Monolithic Power Combiner (PC) is introduced to overcome this limitation and further enhance total achieved system power. The PC sums the power of a collection of SCPAs to a single output, allowing higher output powers at a high efficiency. Benefits, drawbacks and design of SCPA PCs are discussed in this work. The implemented circuit features the combination of four differential SCPAs through a four-way monolithic PC and is simulated to obtain a maximum drain efficiency of 44% at a peak output power of 29dBm on 1.1V supply voltage. Extensive spectrum analysis offers full evaluation of system performances. After exploring state-of-the-art possibilities offered by an advanced 28nm CMOS technology, this work predicts through rigorous theoretical analysis the expected evolution of SCPA performances with the scaling of CMOS Technologies. The encouraging forecast further emphasizes the importance of SCPA circuits for the future of high-performance Wireless Communications

Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

펄스에 의한 동적 부하 변조 기술을 이용한 고효율 선형 송신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 서광석.STRONG push for longer battery life time and growing thermal concerns for the modern 3G/4G mobile terminals lead to an ever-growing need for higher efficiencies from the handset power amplifiers (PAs). Furthermore, as the modulation signal bandwidth is increased and more complex modulation schemes are introduced for higher data rate, the peak-to-average power ratio (PAPR) of signals increases and the PA requires more power back-off to meet the stringent linearity requirement. Therefore, the PA design has to address the challenging task of enhancing the efficiencies in the back-off power levels. In this dissertation, dynamic load modulation (DLM) technique is investigated to boost the efficiency of a PA in the back-off output power level. This technique increases the efficiency by adjusting the PA load impedance according to the magnitude of the envelope signal. It can be categorized into two types, continuous and discrete types. Continuous-type DLM PA changes load impedance continuously by changing the capacitance of varactors used in the load matching circuit. Although the continuous modulation of the load impedance may result in significant efficiency enhancement, difficulties on integration of varactors and complexities on linearization of the PA make it difficult to be applied to the handset PA applications. Discrete-type DLM PA switches the load impedance from one value to another using RF switches. This type has the advantage in the aspect of ease of integration and simplicity in linearization compared to the continuous-type DLM PA, which make it more suited to the handset PA applications. However, the overall efficiency enhancement is quite limited since the PA does not always operate under the optimal load conditions. To overcome the limitation of the existing DLM techniques, a new method of DLM, called pulsed dynamic load modulation (PDLM), is proposed to operate the PA near the optimum impedance across a continuous back-off power range while still benefiting from the advantages offered by the discrete-type DLM PA. PDLM PA combines the concept of Class-S PA with 1-bit discrete load switching. Analytical calculation using simplified equivalent model is well matched with simulation results. To prove the proposed concept, it is implemented by designing and fabricating a prototype PDLM PA at 837 MHz using a 0.32-μm silicon-on-insulator (SOI) CMOS process. The experimental results show the overall PAE improvement for high-PAPR signals such as LTE signals. Several issues caused by the PDLM technique are also discussed such as imperfect pulse tone termination effect and output noise spectrum due to pulse tones. Improving methods are proposed through the further analysis and evaluation. The proposed PA is compared to the envelope tracking (ET) PA which is commonly used to boost efficiency at the back-off output power. Since the proposed concept is realized with low-power control circuits unlike envelope tracking, which requires high-power circuits such as dc-dc converters and linear amplifiers, the PDLM PA concept of this work can provide a potential solution for high-efficiency PAs for the future mobile terminals using wideband modulation signals.Chapter 1. Introduction 1 Chapter 2. Dynamic Load Modulation Technique 8 2.1 Introduction 8 2.2 Continuous-type dynamic load modulation PA 9 2.3 Discrete-type dynamic load modulation PA 14 2.4 Implementation example 15 2.4.1 DLM PA Structure 16 2.4.2 Linearization 23 2.4.3 Experimental Results 25 2.4.4 Conclusion 31 2.5 Limitations 32 2.6 References 33 Chapter 3. A Pulsed Dynamic Load Modulation Technique for High-Efficiency Linear Transmitters 36 3.1 Introduction 36 3.2 Operation Principle of the PDLM PA 38 3.2.1 Concept of the PDLM PA 38 3.2.2 Theoretical Analysis of the PDLM PA 41 3.3 Circuit Design 47 3.3.1 2 stage CMOS PA design 49 3.3.2 High power RF switch design 59 3.3.3 PWM signal generator and switch driver 61 3.4 Experimental Results 63 3.5 Conclusion 76 3.6 References 77 Chapter 4. Discussions 83 4.1 Operation bandwidth of the PDLM PA 83 4.2 Spectral noise reduction method 87 4.3 References 91 Chapter 5. Conclusions 94 5.1 Research Summary 94 5.2 Future Works 95 Abstract in Korean 97 Publications 99Docto

Concurrent Multi-Band Envelope Tracking Power Amplifiers for Emerging Wireless Communications

Emerging wireless communication is shifting toward data-centric broadband services, resulting in employment of sophisticated and spectrum efficient modulation and access techniques. This yields communication signals with large peak-to-average power ratios (PAPR) and stringent linearity requirements. For example, future wireless communication standard, such as long term evolution advanced (LTE-A) require adoption of carrier aggregation techniques to improve their effective modulation bandwidth. The carrier aggregation technique for LTE-A incorporates multiple carriers over a wide frequency range to create a wider bandwidth of up to 100MHz. This will require future power amplifiers (PAs) and transmitters to efficiently amplify concurrent multi-band signals with large PAPR, while maintaining good linearity. Different back-off efficiency enhancement techniques are available, such as envelope tracking (ET) and Doherty. ET has gained a lot of attention recently as it can be applied to both base station and mobile transmitters. Unfortunately, few publications have investigated concurrent multi-band amplification using ET PAs, mainly due to the limited bandwidth of the envelope amplifier. In this thesis, a novel approach to enable concurrent amplification of multi-band signals using a single ET PA will be presented. This thesis begins by studying the sources of nonlinearities in single-band and dual-band PAs. Based on the analysis, a design methodology is proposed to reduce the sources of memory effects in single-band and dual-band PAs from the circuit design stage and improve their linearizability. Using the proposed design methodology, a 45W GaN PA was designed. The PA was linearized using easy to implement, memoryless digital pre-distortion (DPD) with 8 and 28 coefficients when driven with single-band and dual-band signals, respectively. This analysis and design methodology will enable the design of PAs with reduced memory effects, which can be linearized using simple, power efficient linearization techniques, such as lookup table or memoryless polynomial DPD. Note that the power dissipation of the linearization engine becomes crucial as we move toward smaller base station cells, such as femto- and pico-cells, where complicated DPD models cannot be implemented due to their significant power overhead. This analysis is also very important when implementing a multi-band ET PA system, where the sources of memory effects in the PA itself are minimized through the proposed design methodology. Next, the principle of concurrent dual-band ET operation using the low frequency component (LFC) of the envelope of the dual-band signal is presented. The proposed dual-band ET PA modulates the drain voltage of the PA using the LFC of the envelope of the dual-band signal. This will enable concurrent dual-band operation of the ET PA without posing extra bandwidth requirements on the envelope amplifier. A detailed efficiency and linearity analysis of the dual-band ET PA is also presented. Furthermore, a new dual-band DPD model with supply dependency is proposed in this thesis, capable of capturing and compensating for the sources of distortion in the dual-band ET PA. To the best of our knowledge, concurrent dual-band operation of ET PAs using the LFC of the envelope of the dual-band signal is presented for the first time in the literature. The proposed dual-band ET operation is validated using the measurement results of two GaN ET PA prototypes. Lastly, the principle of concurrent dual-band ET operation is extended to multi-band signals using the LFC of the envelope of the multi-band signal. The proposed multi-band ET operation is validated using the measurement results of a tri-band ET PA. To the best of our knowledge, this is the first reported tri-band ET PA in literature. The tri-band ET PA is linearized using a new tri-band DPD model with supply dependency

Digitally-Modulated Transmitter for Wireless Communications

With the increased digital processing capabilities of sub-micron CMOS nodes, pushing the digital world towards the antenna is becoming attractive, enabling higher reconfigurability of the transmitter, therefore, more degrees of freedom to end-users. More specifically, by adopting an RF-DAC (DAC working at RF frequency) instead of the traditional Power Amplifier block allows for increased performance of the whole transmitter. Hence, a polar transmitter is being studied and an implementation in 130 nm CMOS node is expected