A novel genetic algorithm for evolvable hardware

Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures

Digital Circuit Design Through Simulated Evolution (SimE)

Abstract- In this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization of circuits. Results obtained by SimE algorithm are compared to those obtained by Genetic Algorithm (CA)

Double Helix Structure and Finite Persisting Sphere Genetic Algorithm in Designing Digital Circuit Structure

This paper proposes a new approach of chromosome representation in digital circuit design which is Double Helix Structure (DHS). The idea of DHS in chromosome representation is inspired from the nature of the DNA\u27s structure that built up the formation of the chromosomes. DHS is an uncomplicated design method. It uses short chromosome string to represent the circuit structure. This new structure representation is flexible in size where it is not restricted by the conventional matrix structure representation. There are some advantages of the proposed method such as convenience to apply due to the simple formation and flexible structure, less requirement of memory allocation and faster processing time due to the short chromosomes representation. In this paper, DHS is combined with Finite Persisting Sphere Genetic Algorithm (FPSGA) to optimal the digital circuit structure design. The experimental results prove that DHS uses short chromosome string to produce the flexible digital circuit structure and FPSGA further optimal the number of gates used in the structure. The proposed method has better performance compared to other methods

Double Helix Structure and Finite Persisting Sphere Genetic Algorithm in Designing Digital Circuit Structure

This paper proposes a new approach of chromosome representation in digital circuit design which is Double Helix Structure (DHS). The idea of DHS in chromosome representation is inspired from the nature of the DNA\u27s structure that built up the formation of the chromosomes. DHS is an uncomplicated design method. It uses short chromosome string to represent the circuit structure. This new structure representation is flexible in size where it is not restricted by the conventional matrix structure representation. There are some advantages of the proposed method such as convenience to apply due to the simple formation and flexible structure, less requirement of memory allocation and faster processing time due to the short chromosomes representation. In this paper, DHS is combined with Finite Persisting Sphere Genetic Algorithm (FPSGA) to optimal the digital circuit structure design. The experimental results prove that DHS uses short chromosome string to produce the flexible digital circuit structure and FPSGA further optimal the number of gates used in the structure. The proposed method has better performance compared to other methods

Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

Meta-parametric design

Parametric modelling software often maintains an explicit history of design development in the form of a graph. However, as the graph increases in complexity it quickly becomes inflexible and unsuitable for exploring a wide design space. By contrast, implicit low-level rule systems can offer wide design exploration due to their lack of structure, but often act as black boxes to human observers with only initial conditions and final designs cognisable. In response to these two extremes, the authors propose a new approach called Meta-Parametric Design, combining graph-based parametric modelling with genetic programming. The advantages of this approach are demonstrated using two real case-study projects that widen design exploration whilst maintaining the benefits of a graph representation

Fuzzified Ant Colony Optimization Algorithm for Efficient Combinational Circuits Synthesis

Abstract- With the increasing demand for high quality, more efficient, less areaand less power circuits, the problem of logic circuit design has become a multiobjective optimization problem. In this paper, multiobjective optimization of logic circuits based on a fnzzified Ant Colony (ACO) algorithm is presented. The results obtained using the proposed algorithm are compared to those obtained using SIS in terms of area, delay and power for some known circuits. It is shown that the circuits produced by the proposed algorithm are better as compared to those obtained by SIS

A Modified Ant Colony Algorithm for Evolutionary Design of Digital Circuits

Abstract- Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biological organisms. The new paradigm is expected to radically change the synthesis procedures in a way that can help discovering novel designs andor more efficient circuits. In this paper, a multiohjective optimization of logic circuits based on a modified Ant Colony (ACO) algorithm is presented. The performance of the proposed algorithm is evaluated using a set of randomly generated circuits. The results obtained using the proposed algorithm are compared to those obtained using existing ACO-based techniques. It is shown that the designed circuits using the proposed algorithm outperform those of the existing techniques

A Modified Ant Colony Algorithm for Evolutionary Design of Digital Circuits

Abstract- Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biological organisms. The new paradigm is expected to radically change the synthesis procedures in a way that can help discovering novel designs andor more efficient circuits. In this paper, a multiohjective optimization of logic circuits based on a modified Ant Colony (ACO) algorithm is presented. The performance of the proposed algorithm is evaluated using a set of randomly generated circuits. The results obtained using the proposed algorithm are compared to those obtained using existing ACO-based techniques. It is shown that the designed circuits using the proposed algorithm outperform those of the existing techniques