Code density concerns for new architectures

Reducing a program\u27s instruction count can improve cache behavior and bandwidth utilization, lower power consumption, and increase overall performance. Nonetheless, code density is an often overlooked feature in studying processor architectures. We hand-optimize an assembly language embedded benchmark for size on 21 different instruction set architectures, finding up to a factor of three difference in code sizes from ISA alone. We find that the architectural features that contribute most heavily to code density are instruction length, number of registers, availability of a zero register, bit-width, hardware divide units, number of instruction operands, and the availability of unaligned loads and stores. We extend our results to investigate operating system, compiler, and system library effects on code density. We find that the executable starting address, executable format, and system call interface all affect program size. While ISA effects are important, the efficiency of the entire system stack must be taken into account when developing a new dense instruction set architecture

A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures

Scheduling, placement, and routing are important steps in Very Large Scale Integration (VLSI) design. Researchers have developed numerous techniques to solve placement and routing problems. As the complexity of Application Specific Integrated Circuits (ASICs) increased over the past decades, so did the demand for improved place and route techniques. The primary objective of these place and route approaches has typically been wirelength minimization due to its impact on signal delay and design performance. With the advent of Field Programmable Gate Arrays (FPGAs), the same place and route techniques were applied to FPGA-based design. However, traditional place and route techniques may not work for Coarse-Grained Reconfigurable Architectures (CGRAs), which are reconfigurable devices offering wider path widths than FPGAs and more flexibility than ASICs, due to the differences in architecture and routing network. Further, the routing network of several types of CGRAs, including the Field Programmable Object Array (FPOA), has deterministic timing as compared to the routing fabric of most ASICs and FPGAs reported in the literature. This necessitates a fresh look at alternative approaches to place and route designs. This dissertation presents a finite domain constraint-based, delay-aware placement and routing methodology targeting an FPOA. The proposed methodology takes advantage of the deterministic routing network of CGRAs to perform a delay aware placement

ESMD Space Grant Faculty Report

The strength of the Exploration Systems Mission Directorate ESMD Faculty Project lies in its ability to meet National Aeronautics Space Administration NASA's Strategic Educational Outcome 1 by developing a sustainable and long-term integration of student involvement at academic institutions with all NASA Centers. This outcome is achieved by a three-fold approach: 1) by collecting Senior Design projects pertaining to Constellation work performed at each of the ten NASA Centers, 2) by engaging students at Minority Serving Institutions in the art of systems engineering and systems design of technologies required for space exploration, and 3) by identifying potential internships at each Center relative to exploration that provide students who are supported by their institutional Space Grant to engage in on-going mission-level and explorative systems designs. The objectives of the ESMD Faculty Project are to: 1. Aid the Centers (both Education Offices and associated technical organizations) in providing relevant opportunities for the ESMD Space Grant Program to support student and faculty in Senior Design projects 2. Enable better matches between the ESMD work required and what the Space Grant Consortia can do to effectively contribute to NASA programs 3. Provide the Space Grant Consortia an opportunity to strengthen relations with the NASA Centers 4. Develop better collective understanding of the U.S. Space Exploration Policy by the Center, Space Grant, faculty, Education Office, and students 5. Enable Space Grant institution faculty to better prepare their students to meet current and future NASA needs 6. Enable the Center Education Offices to strengthen their ties to their technical organizations and Space Grant Consortia 7. Aid KSC in gaining a greater and more detailed understanding of each of the Center activities Senior Design projects are intended to stimulate undergraduate students on current NASA activities related to lunar, Mars, and other planetary missions and to bring out innovative and novel ideas that can be used to complement those currently under development at respective NASA Centers. Additionally, such academic involvement would better the prospects for graduating seniors to pursue graduate studies and to seek careers in the space industry with a strong sense for systems engineering and understanding of design concepts. Internships, on the other hand, are intended to provide hands-on experience to students by engaging them in diverse state-of-the-art technology development, prototype bread-boarding, computer modeling and simulations, hardware and software testing, and other activities that provide students a strong perspective of NASA's vision and mission in enhancing the knowledge of Earth and space planetary sciences. Ten faculty members, each from a Space Grant Consortium-affiliated university, worked at ten NASA Centers for five weeks between June 2 and July 3, 2008. The project objectives listed above were achieved. In addition to collecting data on Senior Design ideas and identifying possible internships that would benefit NASA/ESMD, the faculty fellows promoted and collected data when required for other ESMD-funded programs and helped the Center's Education Office, as,needed.

A hardware-software codesign framework for cellular computing

Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through hardware mechanisms such as super-scalar execution. However, both these approaches seem to have reached a plateau, mainly due to issues related to design complexity and cost-effectiveness. To face the stabilization of performance of single-threaded processors, the current trend in processor design seems to favor a switch to coarser-grain parallelization, typically at the thread level. In other words, high computational power is achieved not only by a single, very fast and very complex processor, but through the parallel operation of several processors, each executing a different thread. Extrapolating this trend to take into account the vast amount of on-chip hardware resources that will be available in the next few decades (either through further shrinkage of silicon fabrication processes or by the introduction of molecular-scale devices), together with the predicted features of such devices (e.g., the impossibility of global synchronization or higher failure rates), it seems reasonable to foretell that current design techniques will not be able to cope with the requirements of next-generation electronic devices and that novel design tools and programming methods will have to be devised. A tempting source of inspiration to solve the problems implied by a massively parallel organization and inherently error-prone substrates is biology. In fact, living beings possess characteristics, such as robustness to damage and self-organization, which were shown in previous research as interesting to be implemented in hardware. For instance, it was possible to realize relatively simple systems, such as a self-repairing watch. Overall, these bio-inspired approaches seem very promising but their interest for a wider audience is problematic because their heavily hardware-oriented designs lack some of the flexibility achievable with a general purpose processor. In the context of this thesis, we will introduce a processor-grade processing element at the heart of a bio-inspired hardware system. This processor, based on a single-instruction, features some key properties that allow it to maintain the versatility required by the implementation of bio-inspired mechanisms and to realize general computation. We will also demonstrate that the flexibility of such a processor enables it to be evolved so it can be tailored to different types of applications. In the second half of this thesis, we will analyze how the implementation of a large number of these processors can be used on a hardware platform to explore various bio-inspired mechanisms. Based on an extensible platform of many FPGAs, configured as a networked structure of processors, the hardware part of this computing framework is backed by an open library of software components that provides primitives for efficient inter-processor communication and distributed computation. We will show that this dual software–hardware approach allows a very quick exploration of different ways to solve computational problems using bio-inspired techniques. In addition, we also show that the flexibility of our approach allows it to exploit replication as a solution to issues that concern standard embedded applications

The IPS fidelity scale as a guideline to implement Supported Employment

info:eu-repo/semantics/publishe

Solar Decathlon 2014: Techstyle Haus Project Manual

Solar Decathlon 2014 Techstyle Haus Project Manual. The Solar Decathlon competition challenges twenty collegiate teams to design and build sustainable homes that are powered exclusively by solar energy and incorporate sustainable architecture and design. Techstyle Haus is an international Brown University, RISD and University of Applied Sciences Erfurt,Germany collaboration designing a solar passivehaus out of high performance textiles