5 research outputs found

    Microcomputador re-configurável em FPGA para ensino de Arquitetura de Computadores na Ciência da Computação

    Get PDF
    O ensino prático de Arquitetura de Computadores estimula o desenvolvimento tecnológico de hardware no Brasil. Por isso, este artigo propõe um método para o ensino prático de Arquitetura de Computadores na Ciência da Computação. Esse método usa uma arquitetura de microcomputador re-configurável em FPGA, para o ensino dessa disciplina na Computação. Pelo método, microcomputadores são desenvolvidos a partir de uma arquitetura de microcomputador básica de dois bits descrita em esquema elétrico e em VHDL. Os resultados apresentados indicam que o método proposto antecipa o ensino prático de Arquitetura de Computadores para o início das atividades da disciplina e contribui formando recursos humanos especializados no desenvolvimento tecnológico de hardware no País

    A design methodology for application partitioning and architecture development of reconfigurable multiprocessor systems-on-chip

    No full text
    Until today, the efficient partitioning and mapping of applications for multiprocessor systems is a challenging task. The deployment of reconfigurable hardware in this domain helps to meet the application requirements more efficiently due to hardware adaptation at design and runtime, which is not applicable in the traditional multiprocessor domain. To exploit this novel degree of freedom in multiprocessor system-on-chip (MPSoC) technology, a novel design methodology is needed, which helps to hide the complexity of the hardware architecture and its realization alternatives from the developer. This paper shows one approach for such a design methodology for the development of the hardware architecture and the application partitioning and mapping. A novel multistep approach based on hierarchical clustering is used for partitioning of the software application and for configuration of a runtime adaptive multiprocessor system. Furthermore, each application module is then partitioned in a Hardware-Software Codesign process in order to achieve a maximum of performance on the local processors and therefore in general for the MPSoC

    3rd Many-core Applications Research Community (MARC) Symposium. (KIT Scientific Reports ; 7598)

    Get PDF
    This manuscript includes recent scientific work regarding the Intel Single Chip Cloud computer and describes approaches for novel approaches for programming and run-time organization
    corecore