946 research outputs found

    Distributed debugging and tumult

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    A description is given of Tumult (Twente university multicomputer) and its operating system, along with considerations about parallel debugging, examples of parallel debuggers, and the proposed debugger for Tumult. Problems related to debugging distributed systems and solutions found in other distributed debuggers are discussed. The following are the main features of the debugger: it is event based, using a monitor for intercepting these events; record and reply are the main debugging techniques; preprocessing of events is done by programmable filters; the user interface is graphical, using grouping as the main abstraction mechanism. Parts of the debugger, as well as initial versions of the global and local event managers, have been implemented. A slow serial link between the front-end processor and the Tumult system has been replaced by a fast SCSI communication link. The user interface is partly textual, partly graphical. The languages used to implement the debugger are Modula-2 and C. The X Window System and OSF/Motif are used for the graphical user interfac

    On debugging in a parallel system

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    In this paper a description is given of a partly implemented parallel debugger for the Twente University Multicomputer (TUMULT). The system's basic method for exchange of data is message passing. Experience has learned that most programming errors in application software are made in calls to the kernel and the interprocess communication. The debugger is intended to be used for locating bugs at this level in the application software. It is assumed that basic blocks of the debuggee can be debugged using a traditional sequential sourcelevel debugger

    Parallel software tools at Langley Research Center

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    This document gives a brief overview of parallel software tools available on the Intel iPSC/860 parallel computer at Langley Research Center. It is intended to provide a source of information that is somewhat more concise than vendor-supplied material on the purpose and use of various tools. Each of the chapters on tools is organized in a similar manner covering an overview of the functionality, access information, how to effectively use the tool, observations about the tool and how it compares to similar software, known problems or shortfalls with the software, and reference documentation. It is primarily intended for users of the iPSC/860 at Langley Research Center and is appropriate for both the experienced and novice user

    The status of US Teraflops-scale projects

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    The current status of United States projects pursuing Teraflops-scale computing resources for lattice field theory is discussed. Two projects are in existence at this time: the Multidisciplinary Teraflops Project, incorporating the physicists of the QCD Teraflops Collaboration, and a smaller project, centered at Columbia, involving the design and construction of a 0.8 Teraflops computer primarily for QCD.Comment: Contribution to Lattice 94. 7 pages. Latex source followed by compressed, uuenocded postscript file of the complete paper. Individual figures available from [email protected]

    RIOT: a simple graphical assembly tool

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    Errors in the chip assembly process are harder to find than errors in cell design, since they belong to no specific part of the design, but rather to the assembly as a whole. Assembly errors are more costly than call design errors also, since they often go unnoticed until late in the design cycle. Interactive graphic tools typically require that assembly be done with primitive graphical operations, which are inappropriate far the assembly task. Language-based tools give more powerful assembly operations, but remove the two dimensional view of the chip necessary to visualize many assembly operations. Riot is a simple Interactive graphical tool designed to facilitate the assembly of cells into integrated systems. Riot supplies the user with primitive operations of connection -- abutment, routing and stretching - in an interactive graphic environment. Thus, the designer retains full control of the design, including the assignment of positions to instances of cells and the choice of connection mechanism. The computer takes care of the tedious and exacting implementation detail, guaranteeing that connections are actually made. The powerful connection primitives give the user of Riot the ability to quickly assemble a custom chip from a collection of low-level cells. This document provides a discussion of the motivation for Riot and a description of the Riot chip assembly system, its capabilities and its use

    A multiarchitecture parallel-processing development environment

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    A description is given of the hardware and software of a multiprocessor test bed - the second generation Hypercluster system. The Hypercluster architecture consists of a standard hypercube distributed-memory topology, with multiprocessor shared-memory nodes. By using standard, off-the-shelf hardware, the system can be upgraded to use rapidly improving computer technology. The Hypercluster's multiarchitecture nature makes it suitable for researching parallel algorithms in computational field simulation applications (e.g., computational fluid dynamics). The dedicated test-bed environment of the Hypercluster and its custom-built software allows experiments with various parallel-processing concepts such as message passing algorithms, debugging tools, and computational 'steering'. Such research would be difficult, if not impossible, to achieve on shared, commercial systems
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