Hardware simulation of KU-band spacecraft receiver and bit synchronizer, phase 2, volume 1

The acquisition behavior of the PN subsystem of an automatically acquiring spacecraft receiver was studied. A symbol synchronizer subsystem was constructed and integrated into the composite simulation of the receiver. The overall performance of the receiver when subjected to anomalies such as signal fades was evaluated. Potential problems associated with PN/carrier sweep interactions were investigated

RAPID CLOCK RECOVERY ALGORITHMS FOR DIGITAL MAGNETIC RECORDING AND DATA COMMUNICATIONS

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN024293 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Ku-band system design study and TDRSS interface analysis

The capabilities of the Shuttle/TDRSS link simulation program (LinCsim) were expanded to account for radio frequency interference (RFI) effects on the Shuttle S-band links, the channel models were updated to reflect the RFI related hardware changes, the ESTL hardware modeling of the TDRS communication payload was reviewed and evaluated, in LinCsim the Shuttle/TDRSS signal acquisition was modeled, LinCsim was upgraded, and possible Shuttle on-orbit navigation techniques was evaluated

Integrated source and channel encoded digital communication system design study

The analysis of the forward link signal structure for the shuttle orbiter Ku-band communication system was carried out, based on the assumptions of a 3.03 Mcps PN code. It is shown that acquisition requirements for the forward link can be met at the acquisition threshold C/N0 sub 0 value of about 60 dB-Hz, which corresponds to a bit error rate (BER) of about 0.001. It is also shown that the tracking threshold for the forward link is at about 57 dB-Hz. The analysis of the bent pipe concept for the orbiter was carried out, along with the comparative analysis of the empirical data. The complexity of the analytical approach warrants further investigation to reconcile the empirical and theoretical results. Techniques for incorporating a text and graphics capability into the forward link data stream are considered and a baseline configuration is described

G0^0 Electronics and Data Acquisition (Forward-Angle Measurements)

The G$^0$ parity-violation experiment at Jefferson Lab (Newport News, VA) is designed to determine the contribution of strange/anti-strange quark pairs to the intrinsic properties of the proton. In the forward-angle part of the experiment, the asymmetry in the cross section was measured for $\vec{e}p$ elastic scattering by counting the recoil protons corresponding to the two beam-helicity states. Due to the high accuracy required on the asymmetry, the G$^0$ experiment was based on a custom experimental setup with its own associated electronics and data acquisition (DAQ) system. Highly specialized time-encoding electronics provided time-of-flight spectra for each detector for each helicity state. More conventional electronics was used for monitoring (mainly FastBus). The time-encoding electronics and the DAQ system have been designed to handle events at a mean rate of 2 MHz per detector with low deadtime and to minimize helicity-correlated systematic errors. In this paper, we outline the general architecture and the main features of the electronics and the DAQ system dedicated to G$^0$ forward-angle measurements.Comment: 35 pages. 17 figures. This article is to be submitted to NIM section A. It has been written with Latex using \documentclass{elsart}. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment In Press (2007

Optical Communication with Semiconductor Laser Diode

Theoretical and experimental performance limits of a free-space direct detection optical communication system were studied using a semiconductor laser diode as the optical transmitter and a silicon avalanche photodiode (APD) as the receiver photodetector. Optical systems using these components are under consideration as replacements for microwave satellite communication links. Optical pulse position modulation (PPM) was chosen as the signal format. An experimental system was constructed that used an aluminum gallium arsenide semiconductor laser diode as the transmitter and a silicon avalanche photodiode photodetector. The system used Q=4 PPM signaling at a source data rate of 25 megabits per second. The PPM signal format requires regeneration of PPM slot clock and word clock waveforms in the receiver. A nearly exact computational procedure was developed to compute receiver bit error rate without using the Gaussion approximation. A transition detector slot clock recovery system using a phase lock loop was developed and implemented. A novel word clock recovery system was also developed. It was found that the results of the nearly exact computational procedure agreed well with actual measurements of receiver performance. The receiver sensitivity achieved was the closest to the quantum limit yet reported for an optical communication system of this type

Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT-SERDES architecture and presents an overview of the various components that constitute the GBT chipset

Unified S-Band Data Handling System

The data handling portion of the Unified S-Band tracking system consists of three readily separable subsystems. These are: a) the Timing System, b) the Antenna Position Programmer, and c) the Tracking Data Processor. Each of these subsystems is briefly described below

Autonomous Integrated Receive System (AIRS) requirements definition. Volume 3: Performance and simulation

The autonomous and integrated aspects of the operation of the AIRS (Autonomous Integrated Receive System) are discussed from a system operation point of view. The advantages of AIRS compared to the existing SSA receive chain equipment are highlighted. The three modes of AIRS operation are addressed in detail. The configurations of the AIRS are defined as a function of the operating modes and the user signal characteristics. Each AIRS configuration selection is made up of three components: the hardware, the software algorithms and the parameters used by these algorithms. A comparison between AIRS and the wide dynamics demodulation (WDD) is provided. The organization of the AIRS analytical/simulation software is described. The modeling and analysis is for simulating the performance of the PN subsystem is documented. The frequence acquisition technique using a frequency-locked loop is also documented. Doppler compensation implementation is described. The technological aspects of employing CCD's for PN acquisition are addressed