10,384 research outputs found
Cycle-accurate evaluation of reconfigurable photonic networks-on-chip
There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs
Insights into dynamic tuning of magnetic-resonant wireless power transfer receivers based on switch-mode gyrators
Magnetic-resonant wireless power transfer (WPT) has become a reliable contactless source of power for a wide range of applications. WPT spans different power levels ranging from low-power implantable devices up to high-power electric vehicles (EV) battery charging. The transmission range and efficiency of WPT have been reasonably enhanced by resonating the transmitter and receiver coils at a common frequency. Nevertheless, matching between resonance in the transmitter and receiver is quite cumbersome, particularly in single-transmitter multi-receiver systems. The resonance frequency in transmitter and receiver tank circuits has to be perfectly matched, otherwise power transfer capability is greatly degraded. This paper discusses the mistuning effect of parallel-compensated receivers, and thereof a novel dynamic frequency tuning method and related circuit topology and control is proposed and characterized in the system application. The proposed method is based on the concept of switch-mode gyrator emulating variable lossless inductors oriented to enable self-tunability in WPT receiversPeer ReviewedPostprint (published version
Optically reconfigurable 1 x 4 remote node switch for access networks
In this paper we demonstrate an optically controlled 1 x 4 remote node switch, based on membrane InP switches bonded to a silicon-on-insulator circuit. We show that the switch exhibits cross talk better than 25 dB between the output ports, and that the switch operates without receiver sensitivity penalty. Furthermore, the proposed switch architecture allows for optical clock distribution as a means to avoid the need for clock recovery at the receiver side. This is demonstrated in a proof-of-principle experiment where data and clock are sent through a single membrane InP switch
Automated routing and control of silicon photonic switch fabrics
Automatic reconfiguration and feedback controlled routing is demonstrated in an 8×8 silicon photonic switch fabric based on Mach-Zehnder interferometers. The use of non-invasive Contactless Integrated Photonic Probes (CLIPPs) enables real-time monitoring of the state of each switching element individually. Local monitoring provides direct information on the routing path, allowing an easy sequential tuning and feedback controlled stabilization of the individual switching elements, thus making the switch fabric robust against thermal crosstalk, even in the absence of a cooling system for the silicon chip. Up to 24 CLIPPs are interrogated by a multichannel integrated ASIC wire-bonded to the photonic chip. Optical routing is demonstrated on simultaneous WDM input signals that are labelled directly on-chip by suitable pilot tones without affecting the quality of the signals. Neither preliminary circuit calibration nor lookup tables are required, being the proposed control scheme inherently insensible to channels power fluctuations
An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis
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A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning
Nanoscale resistive memories are expected to fuel dense integration of
electronic synapses for large-scale neuromorphic system. To realize such a
brain-inspired computing chip, a compact CMOS spiking neuron that performs
in-situ learning and computing while driving a large number of resistive
synapses is desired. This work presents a novel leaky integrate-and-fire neuron
design which implements the dual-mode operation of current integration and
synaptic drive, with a single opamp and enables in-situ learning with crossbar
resistive synapses. The proposed design was implemented in a 0.18 m CMOS
technology. Measurements show neuron's ability to drive a thousand resistive
synapses, and demonstrate an in-situ associative learning. The neuron circuit
occupies a small area of 0.01 mm and has an energy-efficiency of 9.3
pJspikesynapse
Spin-Based Neuron Model with Domain Wall Magnets as Synapse
We present artificial neural network design using spin devices that achieves
ultra low voltage operation, low power consumption, high speed, and high
integration density. We employ spin torque switched nano-magnets for modelling
neuron and domain wall magnets for compact, programmable synapses. The spin
based neuron-synapse units operate locally at ultra low supply voltage of 30mV
resulting in low computation power. CMOS based inter-neuron communication is
employed to realize network-level functionality. We corroborate circuit
operation with physics based models developed for the spin devices. Simulation
results for character recognition as a benchmark application shows 95% lower
power consumption as compared to 45nm CMOS design
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