Design of high-linearity PVT-robust dynamic amplifier

Modern electronic device market demands high power-efficiency, high-speed, and high-resolution analog-to-digital converters (ADC). Amplifiers be-come increasingly significant in the high-performance ADC design. Dynamic amplifier stands out for its low power consumption feature. However, the process-voltage-temperature (PVT) variation and limited linearity prevent it from wide usage. This thesis presents a high-linearity and PVT-robust dynamic amplifier. It implements the capacitively degenerated linearization (CDL) method to achieve high linearity. Furthermore, it combines a PVT-sensing amplifier and a voltage-to-time (V2T) converter as the control timer. Once the foreground calibration is done, the proposed dynamic amplifier will track the PVT variation and provide high-linearity and stable gain. Compared to the conventional CDL dynamic amplifier and the PVT-stabilized dynamic amplifier, this design suffers from less gain variation over PVT fluctuation while exhibiting high linearity. Therefore, it suits the application of the pipeline ADC and other types of ADC. A design prototype in schematic level is implemented in 40nm TSMC CMOS technology. The simulation results indicate that the circuit provides less than −80dB total-harmonics-distortion (THD), ranging from−15°C to 100°C with 140mV peak-to-peak differential sinusoidal input. When the supply voltage varies from 1.15V to 1.25V, the gain variation of this design is within ±2.5% and the THD is less than −75dB.Electrical and Computer Engineerin

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Design of a CMOS chopper instrumentation amplifier with rail-to-rail input and output ranges

This thesis deals with the design of a current feedback instrumentation amplifier, optimized for the readout of thermal sensors. This topology stands out for its excellent CMRR and the predisposition to feature low frequency error reduction techniques. Versatility is a main target for this work: 1 kHz bandwidth and Rail-To-Rail input common mode range allow the readout of a wide variety of sensors. Chopper modulation is used to reduce offset and flicker noise, achieving a 19 nV/sqrt(Hz) RTI noise density and a flicker corner frequency of less than 10 mHz. A low total output noise power is achieved as well, reaching an ENOB of 12 bits with less than 350 µA current consumption. The peculiar issue for this architecture, that is gain error, is solved by means of Port Swapping technique, together with an input Common Mode Equalization. Chopped offset and Port Swapping ripple are completely filtered away by a third order Butterworth State Variable low pass filter, implemented with Gm-C integrators

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Linearity and Noise Improvement Techniques Employing Low Power in Analog and RF Circuits and Systems

The implementation of highly integrated multi-bands and multi-standards reconfigurable radio transceivers is one of the great challenges in the area of integrated circuit technology today. In addition the rapid market growth and high quality demands that require cheaper and smaller solutions, the technical requirements for the transceiver function of a typical wireless device are considerably multi-dimensional. The major key performance metrics facing RFIC designers are power dissipation, speed, noise, linearity, gain, and efficiency. Beside the difficulty of the circuit design due to the trade-offs and correlations that exist between these parameters, the situation becomes more and more challenging when dealing with multi-standard radio systems on a single chip and applications with different requirements on the radio software and hardware aiming at highly flexible dynamic spectrum access. In this dissertation, different solutions are proposed to improve the linearity, reduce the noise and power consumption in analog and RF circuits and systems. A system level design digital approach is proposed to compensate the harmonic distortion components produced by transmitter circuits’ nonlinearities. The approach relies on polyphase multipath scheme uses digital baseband phase rotation pre-distortion aiming at increasing harmonic cancellation and power consumption reduction over other reported techniques. New low power design techniques to enhance the noise and linearity of the receiver front-end LNA are also presented. The two proposed LNAs are fully differential and have a common-gate capacitive cross-coupled topology. The proposed LNAs avoids the use of bulky inductors that leads to area and cost saving. Prototypes are implemented in IBM 90 nm CMOS technology for the two LNAs. The first LNA covers the frequency range of 100 MHz to 1.77 GHz consuming 2.8 mW from a 2 V supply. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB while the input return loss is greater than 10 dB across the entire band. The second LNA covers the frequency range of 100 MHz to 1.6 GHz. A 6 dBm third-order input intercept point, IIP3, is measured at the maximum gain frequency. The core consumes low power of 1.55 mW using a 1.8 V supply. The measured voltage gain is 15.5 dB with a 3-dB bandwidth of 1.6 GHz. The LNA has a minimum NF of 3 dB across the whole band while achieving an input return loss greater than 12 dB. Finally, A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth (GBW). The OTA is fabricated on the AMI 0.5 um CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB till 10 KHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers a very low current consumption of 25 uA from a 3.3 V supply

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Development of a sub-miniature acoustic sensor for wireless monitoring of heart rate

This thesis presents the development of a non-invasive, wireless, low-power, phonocardiographic (PCG) or heart sound sensor platform suitable for long-term monitoring of heart function. The core of this development process involves a study of the feasibility of this conceptual system and the development of a prototype mixed-signals integrated circuit (IC) to form the integral component of the proposed sensor. The feasibility study of the proposed long-term monitoring sensor is divided into two main parts. The first part of the study investigates the technological aspect of the conceptual system, via a system level design. This is to prove the technological or operational feasibility of the system, where the system can be built completely using discrete, off-the-shelf electronics components to satisfy the size, power consumption, battery life and operational requirements of the sensor platform. The second part of the study concentrates on the post-processing of the heart sounds and murmurs or PCG data recorded. This is where a number of different de-noising algorithms are studied and their relative performance compared when applied to a variety of different noisy heart sound signals that would likely be acquired using the proposed sensor in everyday life. This was done to demonstrate the functional feasibility of the proposed system, where the ambient acoustic noise in the recorded PCG data can be effectively suppressed and therefore meaningful analysis of heart function i.e. heart rate, can be performed on the data. After the feasibility of the conceptual system has been demonstrated, the final part of this thesis discusses the synthesis and testing of a 0.35 μm CMOS technology prototype mixed analog-digital integrated circuit (IC) to miniaturise part of this sensor platform outlined in the system level design, conducted in the earlier part of this thesis, to achieve the objective specifications – in terms of the size and power consumption. A new implementation of the multi-tanh triplet transconductor is introduced to construct a pair of 100 nW analogue 4th order Gm-C signal conditioning filters. Furthermore, a 7 μW digital circuit was designed to drive the analog-to-digital conversion cycle of the Linear Technology LTC1288 ADC and synchronise the ADC’s output to generate the Manchester encoded data compatible with the Holt Integrated Circuit HI-15530 Manchester Encoder/Decoder

Low-Power Integrated Circuits For Biomedical Applications

With thousands new cases of spinal cord injury reported everyday, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs, such a state severely deteriorates the patients' quality of life and may even lead to additional medical conditions. Therefore, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient's brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts, having high spatial resolution and signal to noise ratio, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted. To implement a fully implantable system, low-power and miniaturized electronics are needed to reduced heat generation, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system's components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system, namely, ultra low-power brain signal acquisition front-ends, a low-power and inductorless MedRadio transceiver, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillator generates the reference signal for other system's components such as analog to digital converter. Novel techniques to improve important performance parameters (power consumption, low noise operation and interference resilience) have been introduced. Electrical, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design