130 research outputs found
Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.
In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge.
On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques.
This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ÎÎŁ modulator
Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters
The profound digitization of modern microelectronic modules made Analog-to-
Digital converters (ADC) key components in many systems. With resolutions up to
14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for
a wide range of applications such as instrumentation, communications and consumer
electronics. However, while past work focused on enhancing the performance of the
pipeline ADC from an architectural standpoint, little has been done to individually
address its fundamental building blocks. This work aims to achieve the latter by
proposing design techniques to improve the performance of these blocks with minimal
power consumption in low voltage environments, such that collectively high
performance is achieved in the pipeline ADC.
Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as
an enhancement to the general performance of the conventional folded cascode. Tested
in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary
Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the
bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon
area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage
environments using a dual level common mode feedback (CMFB) circuit, and amplifier
differential offsets up to 50mV are effectively cancelled. Together with the RFC, the
dual level CMFB was used to implement a sample and hold amplifier driving a singleended
load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is
achieved. Finally a power conscious technique is proposed to reduce the kickback noise
of dynamic comparators without resorting to the use of pre-amplifiers. When all
techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in
Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2
effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal.
The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to
recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline
ADC uses the least power per conversion rated at 0.45pJ/conversion-step
Advanced Technology Large-Aperture Space Telescope (ATLAST): A Technology Roadmap for the Next Decade
The Advanced Technology Large-Aperture Space Telescope (ATLAST) is a set of
mission concepts for the next generation of UVOIR space observatory with a
primary aperture diameter in the 8-m to 16-m range that will allow us to
perform some of the most challenging observations to answer some of our most
compelling questions, including "Is there life elsewhere in the Galaxy?" We
have identified two different telescope architectures, but with similar optical
designs, that span the range in viable technologies. The architectures are a
telescope with a monolithic primary mirror and two variations of a telescope
with a large segmented primary mirror. This approach provides us with several
pathways to realizing the mission, which will be narrowed to one as our
technology development progresses. The concepts invoke heritage from HST and
JWST design, but also take significant departures from these designs to
minimize complexity, mass, or both.
Our report provides details on the mission concepts, shows the extraordinary
scientific progress they would enable, and describes the most important
technology development items. These are the mirrors, the detectors, and the
high-contrast imaging technologies, whether internal to the observatory, or
using an external occulter. Experience with JWST has shown that determined
competitors, motivated by the development contracts and flight opportunities of
the new observatory, are capable of achieving huge advances in technical and
operational performance while keeping construction costs on the same scale as
prior great observatories.Comment: 22 pages, RFI submitted to Astro2010 Decadal Committe
Energy Efficient Pipeline ADCs Using Ring Amplifiers
Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency.
The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversionâstep.
The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversionâstep and 174.9 dB, respectively.
Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd
Advanced CMOS Integrated Circuit Design and Application
The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuitâs key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuitâs
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais råpidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicaçÔes que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia â3D-stackedâ. O empilhamento de chips Ă© relativamente recente e Ă© uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vĂĄrios planos de silĂcio com diferentes
funçÔes poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem â3D-stackedâ com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca ĂĄrea utilizada, de forma a obter-se o melhor rĂĄcio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuiçÔes feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusĂ”es,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
A high frame rate wearable EIT system using active electrode ASICs for lung respiration and heart rate monitoring
A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high- performance current driver capable of up to 6 mApâp output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35-ÎŒm high-voltage process technology. It operates from ±9-V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 Q/frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated
A high frame rate wearable EIT system using active electrode ASICs for lung respiration and heart rate monitoring
A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high- performance current driver capable of up to 6 mApâp output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35-ÎŒm high-voltage process technology. It operates from ±9-V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 Q/frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated
GRB Probes of the High-z Universe with EXIST
The Energetic X-ray Imaging Survey Telescope (EXIST) mission concept is
optimized for study of high-z GRBs as probes of the early Universe. With a High
Energy Telescope (HET) incorporating a 4.5m^2 5-600keV (CZT; 0.6mm pixels)
detector plane for coded aperture imaging a 90deg x 70deg (>10% coding
fraction) field of view with 2' resolution and <20" (90% conf.) positions for
>5 sigma sources, EXIST will perform rapid (<200sec) slews onto GRBs. Prompt
images and spectra are obtained with a co-aligned soft X-ray telescope (SXI;
0.1 - 10keV) and with a 1.1m optical-IR telescope (IRT) simultaneously in 4
bands (0.3 - 0.52micron, 0.52 - 0.9micron, 0.9 - 1.38micron, and 1.38 -
2.3micron). An initial image (100s) will yield prompt identification within the
HET error circle from a <2" prompt SXI position; or from VIS vs. IR dropouts or
variability. An autonomous spacecraft re-point (<30") will then put the GRB on
a 0.3" x 4" slit for either R = 3000 (for AB <21) or R =30 (for AB ~21-25)
prompt spectra over the 0.3 - 0.9 micron and 0.9 - 2.3 micron bands. This will
provide onboard redshifts within ~500-2000sec for most GRBs, reaching z ~20
(for Lyman-alpha breaks) if such GRBs exist, and spectra for studies of the
host galaxy and local re-ionization patchiness as well as intervening cosmic
structure. With ~600 GRBs/yr expected, including ~7-10% expected at z >7, EXIST
will open a new era in studies of the early Universe as well as carry out a
rich program of AGN and transient-source science. An overview of the GRB
science objectives and a brief discussion of the overall mission design and
operations is given, and example high-z GRB IRT spectra are shown. EXIST is
being proposed to the Astro2010 Decadal Survey as a 5 year Medium Class mission
that could be launched as early as 2017.Comment: 7 pages, 5 figures, 1 table; to appear in Proc. Huntsville Gamma-ray
Burst Symposium, AIPC (C. Meegan, N. Gehrels and C. Kouveliotou, eds.), in
pres
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