Bi-directional of a Built-in Test Circuit for Interconnect Defects in Assembled PCBs

Bi-directional of a built-in test circuit is proposed to detect open defects at inputs and output interconnects between ICs and a PCB. The test circuit is based on an electrical characteristic of an inverter gate. A test method is related to supply current which flows to the inverter by providing a test signal to the test circuit. The test signal is generated by an AC voltage signal with a DC offset voltage. The open defects which occur at the interconnects will be detected by the large supply current flows to the inverter. On the other hand, if the defects don't occur, the supply current of the inverter is almost zero. Testability of the test circuit is examined using a Spice simulation. The results show that the open defects at the interconnects can be detected and located

Improved reliability of planar power interconnect with ceramic-based structure

This paper proposes an advanced Si3N4 ceramic-based structure with through vias designed and filled with brazing alloy as a reliable interconnect solution in planar power modules. Finite element (FE) modeling and simulation were first used to predict the potential of using the proposed Si3N4 ceramic-based structure to improve the heat dissipation and reliability of planar interconnects. Power cycling tests and non-destructive microstructural characterization were then performed on Si3N4 ceramic-based structures, flexible printed circuit boards (PCB) and conventional Al wire interconnect samples to evaluate the FE predictions. Both the FE simulations and experimental tests were carried out on single Si diode samples where both the ceramic-based structures and flexible PCBs were bonded on the top sides of Si diodes with eutectic Sn-3.5Ag solder joints. The results obtained demonstrate that Si3N4 ceramic-based structures can significantly improve the reliability of planar interconnects. The experimental average lifetimes and FE simulated maximum creep strain accumulations for the ceramic-based structure and flexible PCB interconnect samples can reasonably be fitted to existing lifetime models for Sn-3.5Ag solder joints. Discrepancies between the models and experimental results can be attributed to defects and poor filling of the brazing alloy in the vias through the Si3N4 ceramic

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Multifunctional vertical interconnections of multilayered flexible substrates for miniaturised POCT devices

Point-of-care testing (POCT) is an emerging technology which can lead to an eruptive change of lifestyle and medication of population against the traditional medical laboratory. Since living organisms are intrinsically flexible and malleable, the flexible substrate is a necessity for successful integration of electronics in biological systems that do not cause discomfort during prolonged use. Isotropic conductive adhesives (ICAs) are attractive to wearable POCT devices because ICAs are environmentally friendly and allow a lower processing temperature than soldering which protects heat-sensitive components. Vertical interconnections and optical interconnections are considered as the technologies to realise the miniaturised high-performance devices for the future applications. This thesis focused on the multifunctional integration to enable both electrical and optical vertical interconnections through one via hole that can be fabricated in flexible substrates. The functional properties of the via and their response to the external loadings which are likely encountered in the POCT devices are the primary concerns of this PhD project. In this thesis, the research of curing effect on via performance was first conducted by studying the relationship between curing conditions and material properties. Based on differential scanning calorimetry (DSC) analysis results, two-parameter autocatalytic model (Sestak-Berggren model) was established as the most suitable curing process description of our typical ICA composed of epoxy-based binders and Ag filler particles. A link between curing conditions and the mechanical properties of ICAs was established based on the DMA experiments. A series of test vehicles containing vias filled with ICAs were cured under varying conditions. The electrical resistance of the ICA filled vias were measured before testing and in real time during thermal cycling tests, damp heat tests and bending tests. A simplified model was derived to represent rivet-shaped vias in the flexible printed circuit boards (FPCBs) based on the assumption of homogenous ICAs. An equation was thus proposed to evaluate the resistance of the model. Vias with different cap sizes were also tested, and the equation was validated. Those samples were divided into three groups for thermal cycling test, damp heat ageing test and bending test. Finite element analysis (FEA) was used to aid better understanding of the electrical conduction mechanisms. Based on theoretical equation and simulation model, the fistula-shape ICA via was fabricated in flexible PCB. Its hollow nature provides the space for integrations of optical or fluidic circuits. Resistance measurements and reliability tests proved that carefully designed and manufactured small bores in vias did not comprise the performance. Test vehicles with optoelectrical vias were made through two different approaches to prove the feasibility of multifunctional vertical interconnections in flexible substrates. A case study was carried out on reflection Photoplethysmography (rPPG) sensors manufacturing, using a specially designed optoelectronic system. ICA-based low-temperature manufacture processes were developed to enable the integration of these flexible but delicate substrates and components. In the manufacturing routes, a modified stencil printing setup, which merges two printing-curing steps (vias forming and components bonding) into one step, was developed to save both time and energy. The assembled probes showed the outstanding performance in functional and physiological tests. The results from this thesis are anticipated to facilitate the understanding of ICA via conduction mechanism and provide an applicable tool to optimise the design and manufacturing of optoelectrical vias

Reliability of CGA/LGA/HDI Package Board/Assembly (Revision A)

This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of 55 C to maximum temperatures of either 100 C or 125 C with slow ramp-up rate (3 C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects' use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight

Reliability of CGA/LGA/HDI Package Board/Assembly (Final Report)

Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented

FEASIBILITY INVESTIGATION OF FAULT DIAGNOSIS USING ELECTROMAGNETIC ANALYSIS OF PLANAR STRUCTURES

Nowadays, circuit design technologies have progressively advanced to cope with the high performance of the electronic components. With the circuit design advancement,the technology for IC fabrication has moved to deep submicron era. As the circuit sizes continue to scale down to nanoscale, the number of transistors and interconnects on the circuits tends to grow as well. This challengesthe circuit testing by introducing high number of possible faults on the circuit. Consequently, the product qualitycontrol has become more challenging. The product quality could drop significantly ifthe circuits are not designed to be testable

Glass multilayer bonding for high density interconnect substrates

The aim of this research was the investigation of bonding borosilicate glass sheets, its trade mark CMZ, 100μm thickness, to create multilayer substrates capable of supporting high-density electrical interconnections. CMZ glass was chosen as it has a coefficient of thermal expansion that is close to that of silicon, thereby minimising thermal stresses in assemblies generated by manufacturing processes or service conditions. Two different methods of bonding the glass were used in this study; pressure assisted low temperature bonding (PALTB), and water glass bonding, using Sodium Trisilicate (Na2Si3O7) solution. These two bonding methods have already been applied in electronics manufacturing applications, such as silicon wafer bonding and multichip modules (MCMs). However, glass-to-glass bonding is a relatively new subject and this study is an attempt to standardise bonding processes. Additionally, the concept of using glass as a multilayer substrate provides a foundation for further exploration by other investigators. Initial tests that were carried out before standardising the procedures for these two methods showed that a two-stage bonding process provided optimum results. A preliminary stage commenced by placing the cleaned (using Decon 90 solution) samples in a vacuum oven for 15 minutes, then heating at 100oC for 1hr. The permanent stage was then achieved by heating the samples in a conventional oven at temperatures from 200 to 400oC, for different periods. At this stage, the main difference between the two methods was the application of pressure (1-2MPa) during heating of the PALTB samples. To evaluate the quality of the bonds, qualitative tests such as visual, optical microscope and dye penetrant were used. In addition, to estimate the strength and the rigidity of the interlayer bonds, two quantitative tests, comprising of deflection under cyclic stresses and crack opening were used. Thermal cycling and humidity tests were also used to assess resistance of the bonds to environmental effects. The results showed that heating to 100oC was insufficient to enhance the bonds, as occasionally a sudden increase of deflection was observed indicating slippage/delamination. These bonds were enhanced during the permanent bonding stage by heating to 300oC in PALTB, under a pressure of 1-2MPa. The crack-opening test showed that the delamination distances of the bonds in the permanent stage were lower than that for preliminary bonding in both bonding methods. The delamination distances from the crack opening tests were used to calculate the strain energy release rate (GIC) and fracture toughness (KIC) values of the interlayers. The results showed that the KIC values of the permanent PALTB and water glass interlayers were higher than 1MPa.m0.5, while the KIC value of the CMZ glass, determined by linear elastic fracture mechanics, was around 0.8MPa.m0.5. The optical observations revealed that the prepared bonded sheets did not delaminate or break after thermal cycling and humidity tests