Implementation of mean-timing and subsequent logic functions on an FPGA

This article describes the implementation of a mean-timer and coincidence logic on a Virtex-5 FPGA for trigger purposes in a particle physics experiment. The novel feature is that the mean-timing and the coincidence logic are not synchronized with a clock which allows for a higher resolution of approximately 400 ps, not limited by a clock frequency.Comment: 15 pages, 11 figure

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2 . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Keywords: TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronic

A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner

Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 $\mu{} m$ thick die. The target timing resolution is 30 ps RMS for electrons from the conversion of 511 keV photons. A novel synchronization scheme using a patent-pending TDC is used to allow the synchronization of 1.6 million channels across almost 2000 different chips at picosecond-level. A full-featured demonstrator chip with a 3x10 matrix of 500x500 $\mu{} m^{2}$ pixels was produced to validate each block. Its design and experimental results are presented here

A novel synchronizer for a 17.9ps Nutt Time-to-Digital Converter implemented on FPGA

The evolution of Field-Programmable Gate Array (FPGA) technology triggered the appearance of FPGAs with higher operating frequencies and large number of resources. Simultaneously, the evolution of the FPGAs design tools has simplified the development process, reducing the time to market. These factors made FPGA platforms attractive for several applications, including time-of-flight applications that require the implementation of Time-to-Digital Converters (TDC). This work presents a Nutt TDC, based on a coarse counter and a Tapped Delay Line, with 17.9 picoseconds resolution and 5.4 LSB differential nonlinearity (DNL), implemented in a Xilinx Zynq-7000 FPGA, to be used on LiDAR applications and pull-in time measuring in MEMS accelerometers systems.This work was supported by a Portuguese Scholarship from FCT - Fundação para a Ciência e Tecnologia and Bosch Car Multimedia, under the Advanced Engineering Systems for Industry (AESI) doctoral program. (Scholarship ID: PDE/BDE/114562/2016) and COMPETE and FCT: POCI- 01-0145-FEDER-007043 within the Project Scope: UID/CEC/00319/201

Gray-code TDC with improved linearity and scalability for LiDAR applications

This paper presents a TDC architecture based on a gray code oscillator with improved linearity, for FPGA implementations. The proposed architecture introduces manual routing as a method to improve the TDC linearity and precision, by controlling the gray code oscillator Datapath, which also reduces the need for calibration mechanisms. Furthermore, the proposed manual routing procedure improves the performance homogeneity across multiple TDC channels, enabling the use of the same calibration module across multiple channels, if further improved precision is required. The proposed TDC channel uses only 16 FPGA logic resources (considering the Xilinx 7 series platform), making it suitable for applications where a large number of measurement channels are required. To validate the proposed architecture and routing procedure, two channels were integrated with a coarse counter, a FIFO memory and an AXI interface, to assemble the pulse measurement unit. A comparison between the default routing implementation and the proposed manual routing has been performed, shown an improvement of 27% on the overall TDC single-shot precision. The implemented TDC achieved a 380 ps RMS resolution, a maximum DNL of 0.38 LSB and a peak-to-peak INL of 0.69 LSB, corresponding to a 21.7% and 70.4% improvement, respectively, when compared to the default design approach.FCT - Fundação para a Ciência e a Tecnologia(037902

HRFlexToT: A High Dynamic Range ASIC for Time-of-Flight Positron Emission Tomography

Abstract: Time-of-Flight positron emission tomography scanners demand fast and efficient photo sensors and scintillators coupled to fast readout electronics. This article presents the high resolution flexible Time-over-Threshold (HRFlexToT), a 16-channel application-specific-integrated circuit for silicon photomultipliers (SiPM) anode readout manufactured using XFAB 0.18- μm CMOS technology. The main features of the HRFlexToT are a linear Time-over-Threshold with an extended dynamic range (10 bits) for energy measurement, low power consumption (≈ 3.5 mW/ch), and an excellent timing response. The experimental measurements show an energy linearity error of ≈ 3% and an energy resolution of about 12% at 511 keV. Single-photon time resolution measurements performed using an Fondazione Bruno Kessler (FBK) SiPM NUV-HD ( 4×4 mm2 pixel, 40- μm cell) and a Hamamatsu SiPM S13360-3050CS are around 142 and 167 ps full width at half maximum (FWHM), respectively. Coincidence time resolution (CTR) measurements with small cross-section pixelated crystals (LSO:Ce,Ca 0.4%, 2×2×5 mm3) coupled to the same Hamamatsu S13360-3050CS and FBK NUV-HD sensors yield a CTR of 117 ps and 119 ps, respectively. Measurements performed with a large cross-section monolithic crystal (LFS crystal measuring 25×25×20 mm3) and a Hamamatsu SiPM array S13361-6050NE-04 show a CTR of 324 ps FWHM after time-walk and time-skew correction

A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner

Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 µm thick die. The target timing resolution of the scanner is 30 ps RMS for electrons from the conversion of 511 keV photons. The system will include 1.6 million channels across almost 2000 different chips. A full-featured demonstrator chip with a 3×10 matrix of 500×500 µm2 pixels was fabricated to validate each block. Its design and experimental results are presented here. © 2019 CERN

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:

Development of a portable time-domain system for diffuse optical tomography of the newborn infant brain

Conditions such as hypoxic-ischaemic encephalopathy (HIE) and perinatal arterial ischaemic stroke (PAIS) are causes of lifelong neurodisability in a few hundred infants born in the UK each year. Early diagnosis and treatment are key, but no effective bedside detection and monitoring technology is available. Non-invasive, near-infrared techniques have been explored for several decades, but progress has been inhibited by the lack of a portable technology, and intensity measurements, which are strongly sensitive to uncertain and variable coupling of light sources and detector to the scalp. A technique known as time domain diffuse optical tomography (TD-DOT) uses measurements of photon flight times between sources and detectors placed on the scalp. Mean flight time is largely insensitive to the coupling and variation in mean flight time can reveal spatial variation in blood volume and oxygenation in regions of brain sampled by the measurements. While the cost, size and high power consumption of such technology have hitherto prevented development of a portable imaging system, recent advances in silicon technology are enabling portable and low-power TD-DOT devices to be built. A prototype TD-DOT system is proposed and demonstrated, with the long-term aim to design a portable system based on independent modules, each supporting a time-of-flight detector and a pulsed source. The operation is demonstrated of components that can be integrated in a portable system: silicon photodetectors, integrated circuit-based signal conditioning and time detection -- built using a combination of off-the-shelf components and reconfigurable hardware, standard computer interfaces, and data acquisition and calibration software. The only external elements are a PC and a pulsed laser source. This thesis describes the design process, and results are reported on the performance of a 2-channel system with online histogram generation, used for phantom imaging. Possible future development of the hardware is also discussed