A 2.4 GHz CMOS class-F power amplifier with reconfigurable load-impedance matching

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output matching at fundamental frequency without affecting the class-F harmonic tuning up to 3rd harmonic. To the best of our knowledge, this is the first design of a CMOS class-F PA addressed to compensate the effect of load variation. Measurement results for 50 ohm load impedance show a maximum PAE of 26% and maximum output power of 19.2 dBm. The measured total harmonic distortion is 4.9%. Measurement results for load values other than 50 ohm show that PAE increases from 6.5% (not-tuned PA) up to 19.9% (tuned PA) with the same output power (19.2 dBm). Tuning also reduces the adjacent-channel leakage ratio by 5 dB and the spectral regrowth of a Wi-Fi signal at the PA output. The size of the fabricated chip is 1.6 mm × 1.6 mm.Peer ReviewedPostprint (author's final draft

A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

Frequency Multipliers in SiGe BiCMOS for Local Oscillator Generation in D-band Wireless Transceivers

Communications at millimeter-wave (mm-Wave) have drawn a lot of attention in recent years due to the wide available bandwidth which translates directly to higher data transmission capacity. Generation of the transceivers local oscillation (LO) is critical because many contrasting requirements, i.e. tuning range (TR), phase noise (PN), output power, and level of spurious tones, affect the system performance. Differently from what is commonly pursued at Radio Frequency, LO generation with a PLL embedding a VCO at the desired output frequency is not viable at mm-wave. A more promising approach consists of a PLL in the 10-20GHz range, where silicon VCOs feature the best figure of merit, followed by a frequency multiplier. In this thesis, a frequency multiplication chain is investigated to up-convert an LO signal from X-band to D-band by a multiplication factor of 12. The multiplication is done in steps of 3, 2, and 2. A sextupler chip comprises the tripler and the first doubler and the last doubler stage which upconverts the LO signal from E- to D-band is realized in a separate chip, all in a 55nm SiGe BiCMOS technology. The frequency tripler circuit is based on a novel circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a separate break-out chip and consuming 23mW of DC power, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% fractional bandwidth and robustness to power variation of the driving signal over a 15dB range. Including the E-band doubler, the sextupler chip achieves a peak output power of 1.7dBm at 74.4GHz and remains within 2dB variation from 70GHz to 82GHz, corresponding to 16% fractional BW. In this frequency range, the leakages of all harmonics are suppressed by more than 40dBc. The design of the D-band doubler was aimed at delivering high output power with high efficiency and high conversion gain. Toward this end, the efficiency of a push-push pair was improved by a stacked Colpitts oscillator to boost the power conversion gain by 10dB. Moreover, the common-collector configuration keeps separate the oscillator tank from the load, allowing independent optimization of the harmonic conversion efficiency and the load impedance for maximum power delivery. The measured performance of the test chip demonstrated Pout up to 8dBm at 130GHz with 13dB conversion gain and 6.3% Power Added Efficiency

Design and Evaluation of an L-Band Current-Mode Class-D Power Amplifier Integrated Circuit

Power amplifiers (PAs) convert energy from DC to high frequencies in all radio and microwave transmitter systems be they wireless base stations, handsets, radars, heaters, and so on. PAs are the dominant consumers of energy in these systems and, therefore, the dominant sources of system cost and inefficiency. Research has focused on efficient solid-state PA circuit topologies and their optimization since the 1960s. The 2000s saw the current-mode class-D (CMCD) topology, potentially suitable for today\u27s wireless communications systems, show promise in the UHF frequency band. This thesis describes the design and testing of a high-efficiency CMCD amplifier with an integrated driver stage. In addition, analysis of a merged PA-mixer circuit based on the CMCD is provided

Contributing to Second Harmonic Manipulated Continuum Mode Power Amplifiers and On-Chip Flux Concentrators

The current cellular network consumes a staggering 100 TWh of energy every year. In the coming years, millions of devices will be added to the existing network to realize the Internet of Things (IoT), further increasing its power consumption. An RF power amplifier typically consumes a large proportion of the DC power in a wireless transceiver, improving its efficiency has the largest impact on the overall system. Additionally, amplifiers need to demonstrate high linearity and bandwidth to adhere to constraints imposed by wireless standards and to reduce the number of amplifiers required as an amplifier with a broader bandwidth can potentially replace several narrowband amplifiers. A typical approach to improve efficiency is to present an appropriate load at the harmonics generated by the transistor. Recently proposed continuous modes based on harmonic manipulation, such as class B/J continuum, continuous class F (CCF) and continuous class F-1 (CCF-1), have shown the capability of achieving counteracting requirements viz., high efficiency, high linearity, and broad bandwidth (with a fractional bandwidth greater than 30%). In these classes of amplifiers, the second harmonic is manipulated by placing a reactive second harmonic load and the reactive component of the fundamental load is adjusted while keeping a fixed resistive component of the fundamental load. The first contribution of this work is to investigate the reason for amplifiers designed in classes B/J continuum and CCF to achieve high efficiency at back-off and 1dB compression. In this thesis, we demonstrate that the variation of the phase of the current through the non-linear intrinsic capacitances due to the variation of the phase in the continuum of drain voltage waveforms in Class B/J/J* continuum leads to either a reduction or enhancement of intrinsic drain current. Consequently, a subset of voltage waveforms of the class B/J/J* continuum can be used to design amplifiers with higher P1dB, and efficiency at P1dB than in Class B. A simple choice of this subset is demonstrated with a 2.6GHz Class B/J/J* amplifier, achieving a P1dB of 38.1dBm and PAE at P1dB of 54.7%, the highest output power and efficiency at P1dB amongst narrowband linear amplifiers using the CGH40010 reported to date, at a comparable peak PAE of 72%. Secondly, we propose a new formulation for high-efficiency modes of power amplifiers in which both the in-phase and out-of-phase components of the second harmonic of the current are varied, in addition to the second harmonic component of the voltage. A reduction of the in-phase component of the second harmonic of current allows reduction of the phase difference between the voltage and current waveforms, thereby increasing the power factor and efficiency. Our proposed waveforms offer a continuous design space between class B/J continuum and continuous F-1 achieving an efficiency of up to 91% in theory, but over a wider set of load impedances than continuous class F-1. These waveforms require a short at third and higher harmonic impedances, which are easier to achieve at a higher frequency. The load impedances at the second harmonic are reactive and can be of any value between -j∞ and j∞, easing the amplifier design. A trade-off between linearity and efficiency exists in the newly proposed broadband design space, but we demonstrate inherent broadband capability. The fabricated narrowband amplifier using a GaN HEMT CGH40010F demonstrates 75.9% PAE and 42.2 dBm output power at 2.6 GHz, demonstrating a comparable frequency weighted efficiency for this device to that reported in the literature. IoT devices may be deployed in critical applications such as radar or 5G transceivers of an autonomous vehicle and hence need to operate free of failure. Monitoring the drain current of the RF GaN MMIC would allow to optimize the device performance and protect it from surges in its supply current. Galvanic current sensors rely on the magnetic field generated by the current as a non-invasive method of current sensing. In this thesis, our third major contribution is a planar on-chip magnetic flux concentrator, is enhance the magnetic field at the current sensor, thereby improving the current detection capability of a current sensor. Our layout utilizes a discontinuity in a magnetic via, resulting in penetration of the magnetic field into the substrate. The proposed concentrator has a magnetic gain x1.8 in comparison to air. The permeability of the magnetic core required is 500, much lower than that reported in off-chip concentrators, resulting in a significant easing of the specifications of the material properties of the core. Additionally, we explore a novel three-dimensional spiral-shaped magnetic flux concentrator. It is predicted via simulations that this geometry becomes a necessity to enhance the magnetic field for increased form factor as the magnetic field from a single planar concentrator deteriorates as its size increases

Reconfigurable high efficiency class-F power amplifier using CMOS-MEMS technology

The increasing demand for wireless products to be part of our daily lives brings the need for longer battery lifetime, smaller size and lower cost. To increase battery lifetime, high efficiency power amplifiers (PAs) are needed; To make them smaller, integration or reconfiguration is aimed and to reach lower costs, technologies such as CMOS are final goals. However integration of high efficiency PA in CMOS is challenging due to the technology limitations which restricts the achievable output power and efficiency of the PA. In order to bring solutions for the above-mentioned requirements, in this thesis novel reconfigurable class-F PAs, frequency-reconfiguration, CMOS integration, impedance-reconfiguration and CMOS-MEMS implementation are addressed. Starting with a single frequency operation, a novel class-F PA for mobile applications is proposed in which with a proper harmonic tuning structure the need for extra filtering sections is eliminated, achieving an excellent harmonic-suppression level. This topology uses transmission lines and is developed to cover multiple frequency bands for purpose of global coverage with aim of size reduction. Three novel frequency reconfigurable PAs are proposed using MEMS and semiconductor switches to accomplish class-F operation at two frequencies. The main novelty of this structure is that the reconfiguration is done not only at fundamental frequency but also at harmonics with reduced number of tuning elements. Moreover, by proper placement of the switches in the stubs, the maximum voltages over the switches are minimized. The proposed structure overcomes the narrow band performance of class-F, giving an efficiency more than 60% over a 225 MHz and 175 MHz bandwidth at 900 MHz and 1800 MHz respectively. Measurement results showed high performance at both frequency bands giving 69.5% and 57.9% PAE at 900 MHz and 1800 MHz respectively. A novel CMOS class-F PA is proposed that controls up to the 3rd harmonic and can adapt to load variations due to the effect of the human body on mobile phones. It enables the integration of the PA with other devices in a single chip leading to better matching, higher performance, lower cost and smaller size. In addition, it achieves load impedance reconfigurability by using impedance tuner in its output network and by proper tuning of the network, effects of load variation on the performance are compensated. Two designs at 2.4 GHz have been done using either MOS varactors or MEMS variable capacitors as tuning devices. The design using MOS varactors show a maximum measured values of 26% PAE and 19.2 dBm output power for 50 load. For loads other than 50 ohm an improvement of 15% for PAE and 4.4 dB for output power is obtained in comparison to non-tuned one. The second design is done using MEMS variable capacitors integrated in CMOS technology through a mask-less post-processing technique. Simulations results for 50 ohm load show a peak PAE of 32.8% while delivering 18.2 dBm output power.La creixent demanda de productes sense fils en la nostra vida diària requereix dispositius de menor grandària, menor cost i amb una gran autonomia. Per reduir la mida i augmentar l'autonomia és necessari utilitzar sistemes integrats multiestàndard o reconfigurables, amb amplificadors de RF d'alta eficiència, mentre que per reduir el cost, és preferible utilitzar tecnologies econòmiques com CMOS. No obstant això, la integració en CMOS d'amplificadors de radiofreqüència, i en especial, d'alta eficiència, és un repte a causa de les limitacions de la tecnologia que restringeixen la potència de sortida realitzable i l'eficiència de l'amplificador. En aquesta tesi es tracten els diferents reptes anteriorment esmentats, proposant una nova topologia d'amplificador classe-F amb reconfiguració de freqüència, i proposant la integració d'un amplificador classe-F que s¿adapta a impedància de càrrega variable, implementat en CMOS i CMOS-MEMS. Inicialment en la tesi es proposa una topologia d'amplificador classe-F en què, gràcies a una estructura adequada a la xarxa d'adaptació, s¿elimina la necessitat de filtrat extra, aconseguint un nivell de rebuig d'harmònics excel·lent. La topologia proposada utilitza línies de transmissió i s'ha desenvolupat per dues bandes diferents, amb el disseny orientat a implementar un sistema reconfigurable. S'han aconseguit PAE de l'ordre del 80 % amb potències properes a 10 W. Un cop descrita i analitzada la topologia, s'han proposat tres amplificadors reconfigurables per doble banda freqüencial. Per a la reconfiguració s'han utilitzat MEMS i commutadors basats en semiconductors. L'estructura proposada permet la reconfiguració no només en la freqüència fonamental sinó també en els harmònics, però mantenint un nombre reduït d'elements d'ajust. A més, gràcies a l'adequada col·locació dels commutadors en les línies de transmissió, s'ha minimitzat la tensió màxima en els mateixos. Així mateix, l'estructura proposada evita la característica de banda estreta a classe-F, proporcionant una eficiència superior al 60% en unes amplades de banda de 225 MHz i de 175 MHz, per a les banda de 900 MHz i 1800 MHz respectivament. En aquestes bandes, la PAE màxima mesurada és del 69,5% i del 57,9% respectivament. Finalment, s'ha proposat un amplificador integrat en CMOS, classe-F amb control fins al tercer harmònic. L'amplificador proposat incorpora un sintonitzador a la sortida, podent així adaptar-se a variacions d'impedància de càrrega, típiques en dispositius sense fil (WLAN), degudes a l'efecte del cos humà sobre l'antena. La implementació en CMOS permet la integració de l'amplificador de potència amb altres dispositius en un únic xip, donant lloc a una millor adaptació, millor rendiment, menor cost i menor grandària del sistema. A més, gràcies a l'adaptació a les variacions de la impedància de càrrega, permet mantenir el rendiment en diferents rangs d'operació. S'han realitzat dos dissenys de l'amplificador a 2,4 GHz, un basat en varactors MOS i un altre en condensadors variables MEMS. El disseny que utilitza varactors MOS mostra una PAE màxima del 26% i una potència de 19,2 dBm per a càrrega adaptada 50 ohm. Per altres càrregues, gràcies a l'adaptació d'impedància, s'obté una millora de PAE del 15% i de 4,4 dB en potència de sortida. El disseny utilitzant condensadors MEMS s'integra en CMOS gràcies a post-processat sense màscares addicionals. Els resultats de simulació per a 50 ohm mostren una PAE del 32,8% per 18,2 dBm de potència de sortid

Review of Particle Physics

The Review summarizes much of particle physics and cosmology. Using data from previous editions, plus 2,143 new measurements from 709 papers, we list, evaluate, and average measured properties of gauge bosons and the recently discovered Higgs boson, leptons, quarks, mesons, and baryons. We summarize searches for hypothetical particles such as supersymmetric particles, heavy bosons, axions, dark photons, etc. Particle properties and search limits are listed in Summary Tables. We give numerous tables, figures, formulae, and reviews of topics such as Higgs Boson Physics, Supersymmetry, Grand Unified Theories, Neutrino Mixing, Dark Energy, Dark Matter, Cosmology, Particle Detectors, Colliders, Probability and Statistics. Among the 120 reviews are many that are new or heavily revised, including a new review on Machine Learning, and one on Spectroscopy of Light Meson Resonances. The Review is divided into two volumes. Volume 1 includes the Summary Tables and 97 review articles. Volume 2 consists of the Particle Listings and contains also 23 reviews that address specific aspects of the data presented in the Listings

Review of Particle Physics

The Review summarizes much of particle physics and cosmology. Using data from previous editions, plus 2,143 new measurements from 709 papers, we list, evaluate, and average measured properties of gauge bosons and the recently discovered Higgs boson, leptons, quarks, mesons, and baryons. We summarize searches for hypothetical particles such as supersymmetric particles, heavy bosons, axions, dark photons, etc. Particle properties and search limits are listed in Summary Tables. We give numerous tables, figures, formulae, and reviews of topics such as Higgs Boson Physics, Supersymmetry, Grand Unified Theories, Neutrino Mixing, Dark Energy, Dark Matter, Cosmology, Particle Detectors, Colliders, Probability and Statistics. Among the 120 reviews are many that are new or heavily revised, including a new review on Machine Learning, and one on Spectroscopy of Light Meson Resonances. The Review is divided into two volumes. Volume 1 includes the Summary Tables and 97 review articles. Volume 2 consists of the Particle Listings and contains also 23 reviews that address specific aspects of the data presented in the Listings. The complete Review (both volumes) is published online on the website of the Particle Data Group (pdg.lbl.gov) and in a journal. Volume 1 is available in print as the PDG Book. A Particle Physics Booklet with the Summary Tables and essential tables, figures, and equations from selected review articles is available in print, as a web version optimized for use on phones, and as an Android app

Review of Particle Physics

The Review summarizes much of particle physics and cosmology. Using data from previous editions, plus 2,143 new measurements from 709 papers, we list, evaluate, and average measured properties of gauge bosons and the recently discovered Higgs boson, leptons, quarks, mesons, and baryons. We summarize searches for hypothetical particles such as supersymmetric particles, heavy bosons, axions, dark photons, etc. Particle properties and search limits are listed in Summary Tables. We give numerous tables, figures, formulae, and reviews of topics such as Higgs Boson Physics, Supersymmetry, Grand Unified Theories, Neutrino Mixing, Dark Energy, Dark Matter, Cosmology, Particle Detectors, Colliders, Probability and Statistics. Among the 120 reviews are many that are new or heavily revised, including a new review on Machine Learning, and one on Spectroscopy of Light Meson Resonances. The Review is divided into two volumes. Volume 1 includes the Summary Tables and 97 review articles. Volume 2 consists of the Particle Listings and contains also 23 reviews that address specific aspects of the data presented in the Listings. The complete Review (both volumes) is published online on the website of the Particle Data Group (pdg.lbl.gov) and in a journal. Volume 1 is available in print as the PDG Book. A Particle Physics Booklet with the Summary Tables and essential tables, figures, and equations from selected review articles is available in print, as a web version optimized for use on phones, and as an Android app.United States Department of Energy (DOE) DE-AC02-05CH11231government of Japan (Ministry of Education, Culture, Sports, Science and Technology)Istituto Nazionale di Fisica Nucleare (INFN)Physical Society of Japan (JPS)European Laboratory for Particle Physics (CERN)United States Department of Energy (DOE