A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

최적에 가까운 타이밍 적응을 위해 치우친 데이터 레벨과 눈 경사 디텍터를 사용한 최대 눈크기추적 클럭 및 데이터 복원회로 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.이 논문에서는 최소-비트 비트 에러율 (BER)에 대한 최대 눈크기 추적 CDR (MET-CDR)의 설계가 제안되었다. 제안 된 CDR 은 최적의 샘플링 단계를 찾기 위해 반복 절차를 가진 BER 카운터 또는 아이 모니터가 필 요하지 않다. 에러 샘플러 출력에 가중치를 두어 더하여 얻은 치우친 데 이터 레벨 (biased dLev) 은 사전 커서 ISI(pre-cursor ISI) 의 정보도 고려한 눈 높이 정보를 추출한다. 델타 T 만큼의 시간 차이를 둔 지점에서 작동 하는 두 샘플러는 현재 눈 높이와 눈 기울기의 극성을 감지하고, 이 정보 를 통해 제안하는 CDR 은 눈 기울기가 0 이되는 최대 눈 높이로 수렴한 다. 측정 결과는 최대 눈 높이와 최소 BER 의 샘플링 위치가 잘 일치 함 을 보여준다. 28nm CMOS 공정으로 구현된 수신기 칩은 23.5dB 의 채널 손실이 있는 상태에서 26Gb/s 에서 동작 가능하다. 0.25UI 의 아이 오프닝 을 가지며, 87mW 의 파워를 소비한다.In this thesis, design of a maximum-eye-tracking CDR (MET-CDR) for minimum bit error rate (BER) is proposed. The proposed CDR does not require a BER coun-ter or an eye-opening monitor with any iterative procedure to find the near-optimal sampling phase. The biased data-level obtained from the weighted sum of error sampler outputs, UP and DN, extracts the actual eye height information in the presence of pre-cursor ISI. Two samplers operating on two slightly different tim-ings detect the current eye height and the polarity of the eye slope so that the CDR tracks the maximum eye height where the slope becomes zero. Measured results show that the sampling phase of the maximum eye height and that of the mini-mum BER match well. A prototype receiver fabricated in 28 nm CMOS process operates at 26 Gb/s with an eye-opening of 0.25 UI and consumes 87 mW while equalizing 23.5 dB of loss at 13 GHz.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VIII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 RECEIVER FRONT-END 5 2.1.1 CHANNEL 7 2.1.2 EQUALIZER 17 2.1.3 CDR 32 2.2 PRIOR ARTS ON CLOCK RECOVERY 39 2.2.1 BB-CDR 39 2.2.2 BER-BASED CDR 41 2.2.3 EOM-BASED CDR 44 2.3 CONCEPT OF THE PROPOSED CDR 47 CHAPTER 3 MAXIMUM-EYE-TRACKING CDR WITH BIASED DATA-LEVEL AND EYE SLOPE DETECTOR 49 3.1 OVERVIEW 49 3.2 DESIGN OF MET-CDR 50 3.2.1 EYE HEIGHT INFORMATION FROM BIASED DATA-LEVEL 50 3.2.2 EYE SLOPE DETECTOR AND ADAPTATION ALGORITHM 60 3.2.3 ARCHITECTURE AND IMPLEMENTATION 67 3.2.4 VERIFICATION OF THE ALGORITHM 71 3.2.5 ANALYSIS ON THE BIASED DATA-LEVEL 76 3.3 EXPANSION OF MET-CDR TO PAM4 SIGNALING 84 3.3.1 MET-CDR WITH PAM4 84 3.3.2 CONSIDERATIONS FOR PAM4 87 CHAPTER 4 MEASUREMENT RESULTS 89 CHAPTER 5 CONCLUSION 99 APPENDIX A MATLAB CODE FOR SIMULATING RECEIVER WITH MET-CDR 100 BIBLIOGRAPHY 105 초 록 113Docto

Design techniques for low-power multi-GS/s analog-to-digital converters

Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed. A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator’s quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170µm by 85µm. Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 25.8dB with the input signal frequency around DC and 22.8dB around 2GHz, consuming 32.1mW, leading to FoM of 237.3fJ/conversion-step, in a core area less than 800µm by 500µm

A 3.125 Gb/s 5-TAP CMOS Transversal Equalizer

Recently, there is growing interest in high speed circuits for broadband communication, especially in wired networks. As the data rate increases beyond 1 GB/s conventional materials used as communication channels such as PCB traces, coaxial cables, and unshielded twisted pair (UTP) cables, etc. attenuate and distort the transmitted signal causing bit errors in the receiver end. Bit errors make the communication less reliable and in many cases even impossible. The goal of this work was to analyze, and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 µm process and it is capable of compensating up to 20 dB’s of attenuation at 1.5625 GHz for 15 and 20 meters of RG-58 A/U coaxial cables. The equalizer is able to remove 0.5 UI ( 160 ps ) of peak-to-peak jitter and output a signal with 0.1 UI ( 32 ps ) for 15 meters of cable at 3.125 Gb/s. The equalizer draws 18 mA from a 1.8 V power supply which is lower than publications [1, 2] for CMOS transversal equalizers

Digital Centric Multi-Gigabit SerDes Design and Verification

Advances in semiconductor manufacturing still lead to ever decreasing feature sizes and constantly allow higher degrees of integration in application specific integrated circuits (ASICs). Therefore the bandwidth requirements on the external interfaces of such systems on chips (SoC) are steadily growing. Yet, as the number of pins on these ASICs is not increasing in the same pace - known as pin limitation - the bandwidth per pin has to be increased. SerDes (Serializer/Deserializer) technology, which allows to transfer data serially at very high data rates of 25Gbps and more is a key technology to overcome pin limitation and exploit the computing power that can be achieved in todays SoCs. As such SerDes blocks together with the digital logic interfacing them form complex mixed signal systems, verification of performance and functional correctness is very challenging. In this thesis a novel mixed-signal design methodology is proposed, which tightly couples model and implementation in order to ensure consistency throughout the design cycles and hereby accelerate the overall implementation flow. A tool flow that has been developed is presented, which integrates well into state of the art electronic design automation (EDA) environments and enables the usage of this methodology in practice. Further, the design space of todays high-speed serial links is analyzed and an architecture is proposed, which pushes complexity into the digital domain in order to achieve robustness, portability between manufacturing processes and scaling with advanced node technologies. The all digital phase locked loop (PLL) and clock data recovery (CDR), which have been developed are described in detail. The developed design flow was used for the implementation of the SerDes architecture in a 28nm silicon process and proved to be indispensable for future projects

System Design of a Wide Bandwidth Continuous-Time Sigma-Delta Modulator

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed