Design of 28 GHz Low-Power Phased-Array Receiver Frontend in CMOS

This work presents the design and implementation of a low power phased-array receiver frontend at 28 GHz in 65 nm CMOS. The frontend incorporates a low- power low-noise amplifier(LNA) and a passive reflection-type phase shifter (RTPS) capable of providing 360° phase shift with 5-bit phase resolution and low loss variation. Passive phase-shifters in the literature suffer from trade-offs between finite phase resolution, insertion loss and phase shift range, and hence do not provide 360° phase range with uniform, low loss across phase shift settings. The proposed systematic design and load optimization approach leads to the RTPS achieving state-of-art performance in terms of insertion loss with 360° phase shift range, loss variation across phase shift and rms phase error. The low-power LNA is based on a transformer-coupled neutralization architecture that increases gain in each LNA stage, allowing for lower power consumption. The phased-array frontend is designed for Ka-band applications and has been characterized in 65nm CMOS from 26 GHz -30 GHz. The measured RTPS achieves 360 degrees phase shift with -7.75+/-0.3 dB and rms phase error of 0.3 degrees at 28 GHz. The low power phased-array receiver frontend has overall gain of 9.5 dB, gain variation of +/-0.4 dB and measured noise figure of 4.9 dB at 28 GHz. The receiver frontend consumes 10 mW from a 0.9 V supply with phase shifter and LNA active area of 0.16 mm² and 0.32 mm² respectively in 65nm CMOS, demonstrating its suitability for integration into low-power phased array receivers for emerging high data rate 5G wireless communication applications at 28 GHz

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

Array Architectures and Physical Layer Design for Millimeter-Wave Communications Beyond 5G

Ever increasing demands in mobile data rates have resulted in exploration of millimeter-wave (mmW) frequencies for the next generation (5G) wireless networks. Communications at mmW frequencies is presented with two keys challenges. Firstly, high propagation loss requires base stations (BSs) and user equipment (UEs) to use a large number of antennas and narrow beams to close the link with sufficient received signal power. Consequently, communications using narrow beams create a new challenge in channel estimation and link establishment based on fine angular probing. Current mmW system use analog phased arrays that can probe only one angle at the time which results in high latency during link establishment and channel tracking. It is desirable to design low latency beam training by exploring both physical layer designs and array architectures that could replace current 5G approaches and pave the way to the communications for frequency bands in higher mmW band and sub-THz region where larger antenna arrays and communications bandwidth can be exploited. To this end, we propose a novel signal processing techniques exploiting unique properties of mmW channel, and show both theoretically, in simulation and experiments its advantages over conventional approaches. Secondly, we explore different array architecture design and analyze their trade-offs between spectral efficiency and power consumption and area. For comprehensive comparison, we have developed a methodology for optimal design of system parameters for different array architecture candidates based on the spectral efficiency target, and use these parameters to estimate the array area and power consumption based on the circuits reported in the literature. We show that the hybrid analog and digital architectures have severe scalability concerns in radio frequency signal distribution with increased array size and spatial multiplexing levels, while the fully-digital array architectures have the best performance and power/area trade-offs.The developed approaches are based on a cross-disciplinary research that combines innovation in model based signal processing, machine learning, and radio hardware. This work is the first to apply compressive sensing (CS), a signal processing tool that exploits sparsity of mmW channel model, to accelerate beam training of mmW cellular system. The algorithm is designed to address practical issues including the requirement of cell discovery and synchronization that involves estimation of angular channel together with carrier frequency offset and timing offsets. We have analyzed the algorithm performance in the 5G compliant simulation and showed that an order of magnitude saving is achieved in initial access latency for the desired channel estimation accuracy. Moreover, we are the first to develop and implement a neural network assisted compressive beam alignment to deal with hardware impairments in mmW radios. We have used 60GHz mmW testbed to perform experiments and show that neural networks approach enhances alignment rate compared to CS. To further accelerate beam training, we proposed a novel frequency selective probing beams using the true-time-delay (TTD) analog array architecture. Our approach utilizes different subcarriers to scan different directions, and achieves a single-shot beam alignment, the fastest approach reported to date. Our comprehensive analysis of different array architectures and exploration of emerging architectures enabled us to develop an order of magnitude faster and energy efficient approaches for initial access and channel estimation in mmW systems

Micro ring resonators in silicon-on-insulator

Silicon as a platform for photonics has recently seen a very large increase in interest because of its potential to overcome the bandwidth limitations of microprocessor interconnects and the low manufacturing cost given by the high compatibility with the already established micro-electronics industry. There has therefore been a signicant push in silicon photonics research to develop all silicon based optical components for telecoms applications. The work reported in this Thesis is con- cerned with the design, fabrication and characterisation of coupled ring resonators on silicon-on-insulator (SOI) material. The nal objective of this work is to pro- vide a robust and reliable technology for the demonstration of optical buers and delay-lines operating at signal bandwidths up to 100 GHz and in the wavelength region around 1550 nm. The core of the activity focused on the optimisation of the fabrication technology and device geometry to ensure the required device performance for the fabrication of long chains of ring resonators. The nal pro- cess has been optimised to obtain both intra-chip and chip-to-chip reproducibility with a variability of the process controlled at the nanometre scale. This was made possible by careful control of all the variables involved in the fabrication process, reduction of the fabrication complexity, close feature-size repeatability, line-edge roughness reduction, nearly vertical sidewall proles and high uniformity in the ebeam patterning. The best optical propagation losses of the realized waveguides reduced down to 1 dB=cm for 480 220 nm2 rectangular cross-section photonic wires and were consistently kept at typical values of around 1.5 dB=cm. Control of the coupling coecients between resonators had a standard deviation of less than 4 % for dierent realizations and resonance dispersion between resonators was below 50 GHz. All these gures represent the state-of-the-art in SOI photon- ics technology. Considerable eort has also been devoted to the development of ecient thermal electrodes (52 W=GHz) to obtain a recongurable behaviour of the structure and polymer inverse tapers to improve the o-chip coupling (inser- tion losses < 2 dB). Phase-preserving and error-free transmission up to 100 Gbit=s with continuously tunable optical delay up to 200 ps has been demonstrated on the nal integrated systems, proving the compatibility of these devices with advanced modulation formats and high bit-rate transmission systems

MEG Upgrade Proposal

We propose the continuation of the MEG experiment to search for the charged lepton flavour violating decay (cLFV) \mu \to e \gamma, based on an upgrade of the experiment, which aims for a sensitivity enhancement of one order of magnitude compared to the final MEG result, down to the $6 \times 10^{-14}$ level. The key features of this new MEG upgrade are an increased rate capability of all detectors to enable running at the intensity frontier and improved energy, angular and timing resolutions, for both the positron and photon arms of the detector. On the positron-side a new low-mass, single volume, high granularity tracker is envisaged, in combination with a new highly segmented, fast timing counter array, to track positron from a thinner stopping target. The photon-arm, with the largest liquid xenon (LXe) detector in the world, totalling 900 l, will also be improved by increasing the granularity at the incident face, by replacing the current photomultiplier tubes (PMTs) with a larger number of smaller photosensors and optimizing the photosensor layout also on the lateral faces. A new DAQ scheme involving the implementation of a new combined readout board capable of integrating the diverse functions of digitization, trigger capability and splitter functionality into one condensed unit, is also under development. We describe here the status of the MEG experiment, the scientific merits of the upgrade and the experimental methods we plan to use.Comment: A. M. Baldini and T. Mori Spokespersons. Research proposal submitted to the Paul Scherrer Institute Research Committee for Particle Physics at the Ring Cyclotron. 131 Page

Photodetectors

In this book some recent advances in development of photodetectors and photodetection systems for specific applications are included. In the first section of the book nine different types of photodetectors and their characteristics are presented. Next, some theoretical aspects and simulations are discussed. The last eight chapters are devoted to the development of photodetection systems for imaging, particle size analysis, transfers of time, measurement of vibrations, magnetic field, polarization of light, and particle energy. The book is addressed to students, engineers, and researchers working in the field of photonics and advanced technologies

Suspended Optical Graphene Modulators and Multiple-layer Terahertz Waveguides

A development of suspended graphene modulators and layered THz waveguides is conducted by this research. The mainly purpose is to study suspended graphene modulators developed to approach the fundamental limits of graphene and layered THz waveguides for understanding the operating mechanism and possible applications. A detailed review of graphene modulators and THz waveguides is presented. Problems and challenges in these fields are addressed and the proposed research is presented according to the review. The suspended self-biasing graphene modulator reduce the compromise between modulation speed and modulation efficiency, and the proposed design is proven to be very close to the fundamental limits of graphene. A suspended triple-layer graphene modulator enhances the light-graphene interaction further. And the modulation speed is therefore increased further with higher modulation efficiency. Further, a comparison between the suspended graphene double-layer modulator and the sub-wavelength thickness modulator is conducted to show the benefit of suspending. A metal-clad suspended self-biasing graphene modulator shows how nearer fundamental limits design of graphene modulator happens. Layered THz waveguides for the propagation of Surface Plasmon Polaritons (SPPs), filter and sensor applications are presented. The methodology and derivation for this research is shown. The research work presented in this thesis provides a clear roadmap for next generation graphene modulators and THz waveguides

CEPC Technical Design Report -- Accelerator (v2)

The Circular Electron Positron Collider (CEPC) is a large scientific project initiated and hosted by China, fostered through extensive collaboration with international partners. The complex comprises four accelerators: a 30 GeV Linac, a 1.1 GeV Damping Ring, a Booster capable of achieving energies up to 180 GeV, and a Collider operating at varying energy modes (Z, W, H, and ttbar). The Linac and Damping Ring are situated on the surface, while the Booster and Collider are housed in a 100 km circumference underground tunnel, strategically accommodating future expansion with provisions for a Super Proton Proton Collider (SPPC). The CEPC primarily serves as a Higgs factory. In its baseline design with synchrotron radiation (SR) power of 30 MW per beam, it can achieve a luminosity of 5e34 /cm^2/s^1, resulting in an integrated luminosity of 13 /ab for two interaction points over a decade, producing 2.6 million Higgs bosons. Increasing the SR power to 50 MW per beam expands the CEPC's capability to generate 4.3 million Higgs bosons, facilitating precise measurements of Higgs coupling at sub-percent levels, exceeding the precision expected from the HL-LHC by an order of magnitude. This Technical Design Report (TDR) follows the Preliminary Conceptual Design Report (Pre-CDR, 2015) and the Conceptual Design Report (CDR, 2018), comprehensively detailing the machine's layout and performance, physical design and analysis, technical systems design, R&D and prototyping efforts, and associated civil engineering aspects. Additionally, it includes a cost estimate and a preliminary construction timeline, establishing a framework for forthcoming engineering design phase and site selection procedures. Construction is anticipated to begin around 2027-2028, pending government approval, with an estimated duration of 8 years. The commencement of experiments could potentially initiate in the mid-2030s.Comment: 1106 page