System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Radio frequency front-end circuits for W-CDMA direct conversion receiver

Master'sMASTER OF ENGINEERIN

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

Radio frequency circuits for wireless receiver front-ends

The beginning of the 21st century sees great development and demands on wireless communication technologies. Wireless technologies, either based on a cable replacement or on a networked environment, penetrate our daily life more rapidly than ever. Low operational power, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver??s front-end circuits play an important role in faithfully recovering the information transmitted through the wireless channel. Bluetooth is a short-range cable replacement wireless technology. A Bluetooth receiver architecture was proposed and designed using a pure CMOS process. The front-end of the receiver consists of a low noise ampli&#64257;er (LNA) and mixer. The intermediate frequency was chosen to be 2MHz to save battery power and alleviate the low frequency noise problem. A conventional LNA architecture was used for reliability. The mixer is a modi&#64257;ed Gilbert-cell using the current bleeding technique to further reduce the low frequency noise. The front-end draws 10 mA current from a 3 V power supply, has a 8.5 dB noise &#64257;gure, and a voltage gain of 25 dB and -9 dBm IIP3. A front-end for dual-mode receiver is also designed to explore the capability of a multi-standard application. The two standards are IEEE 802.11b and Bluetooth. They work together making the wireless experience more exciting. The front-end is designed using BiCMOS technology and incorporating a direct conversion receiver architecture. A number of circuit techniques are used in the front-end design to achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a 5.5 dB noise &#64257;gure, 33 dB voltage gain and -13 dBm IIP3. Besides the system level contributions, intensive studies were carried out on the development of quality LNA circuits. Based on the multi-gated LNA structure, a CMOS LNA structure using bipolar transistors to provide linearization is proposed. This LNA con&#64257;guration can achieve comparable linearity to its CMOS multi-gated counterpart and work at a higher frequency with less power consumption. A LNA using an on-chip transformer source degeneration is proposed to realize input impedance matching. The possibility of a dual-band cellular application is studied. Finally, a study on ultra-wide band (UWB) LNA implementation is performed to explore the possibility and capability of CMOS technology on the latest UWB standard for multimedia applications

5 GHz Optical Front End in 0.35um CMOS

With the advantages of low cost, low power consumption, high reliability and potential for large scale integration, CMOS monolithically integrated active pixel chips have significant application in optical sensing systems. The optical front end presented in this thesis will have application in Optical Scanning Acoustic Microscope System (O-SAM), which involves a totally non-contact method of acquiring images of the interaction between surface acoustic waves (SAWs) and a solid material to be characterized. In this work, an ultra fast optical front-end using improved regulated cascade scheme is developed based on AMS 0.35mm CMOS technology. The receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p+ junctions as the active region, the integrated photodiode operates up to 4.9 GHz with no process modification. Its responsivity was measured to be 0.016 A/W. With multi-inductive-series peaking technique, the improved ReGulated-Cascade (RGC) transimpedance amplifier achieves an experimentally measured -3dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dBW, which is the fastest reported TIA in CMOS 0.35mm technology. The 5 GHz Gilbert cell mixer produces a conversion gain of 11 dB, which greatly minimized the noise contribution from the IF stage. The noise figure and input IIP3 of the mixer were measured to be 15.7 dB and 1.5 dBm, respectively. The IF amplifier and output buffer pick up and further amplify the signal for post processing. The optical front end demonstrates a typical equivalent input noise current of 35 pA=pHz at 5 GHz, and a total transimpedance gain of 83 dB ohm whileconsuming a total current of 40 mA from 3.3 V power supply. The -3 dB bandwidth for the optical front end was measured to be 4.9 GHz. All the prototype chips, including the optical front end, and the individual circuits including the photodiode, TIA, mixer were probe-tested and all the measurements were taken with Anritsu VNA 37397D and Anritsu spectrum analyser MS2721A

5 GHz Optical Front End in 0.35um CMOS

With the advantages of low cost, low power consumption, high reliability and potential for large scale integration, CMOS monolithically integrated active pixel chips have significant application in optical sensing systems. The optical front end presented in this thesis will have application in Optical Scanning Acoustic Microscope System (O-SAM), which involves a totally non-contact method of acquiring images of the interaction between surface acoustic waves (SAWs) and a solid material to be characterized. In this work, an ultra fast optical front-end using improved regulated cascade scheme is developed based on AMS 0.35mm CMOS technology. The receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p+ junctions as the active region, the integrated photodiode operates up to 4.9 GHz with no process modification. Its responsivity was measured to be 0.016 A/W. With multi-inductive-series peaking technique, the improved ReGulated-Cascade (RGC) transimpedance amplifier achieves an experimentally measured -3dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dBW, which is the fastest reported TIA in CMOS 0.35mm technology. The 5 GHz Gilbert cell mixer produces a conversion gain of 11 dB, which greatly minimized the noise contribution from the IF stage. The noise figure and input IIP3 of the mixer were measured to be 15.7 dB and 1.5 dBm, respectively. The IF amplifier and output buffer pick up and further amplify the signal for post processing. The optical front end demonstrates a typical equivalent input noise current of 35 pA=pHz at 5 GHz, and a total transimpedance gain of 83 dB ohm whileconsuming a total current of 40 mA from 3.3 V power supply. The -3 dB bandwidth for the optical front end was measured to be 4.9 GHz. All the prototype chips, including the optical front end, and the individual circuits including the photodiode, TIA, mixer were probe-tested and all the measurements were taken with Anritsu VNA 37397D and Anritsu spectrum analyser MS2721A

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Innovative Design and Realization of Microwave and Millimeter-Wave Integrated circuits

Ph.DDOCTOR OF PHILOSOPH

MMIC-based Low Phase Noise Millimetre-wave Signal Source Design

Wireless technology for future communication systems has been continuously evolving to meet society’s increasing demand on network capacity. The millimetre-wave frequency band has a large amount of bandwidth available, which is a key factor in enabling the capability of carrying higher data rates. However, a challenge with wideband systems is that the capacity of these systems is limited by the noise floor of the local oscillator (LO). The LO in today’s communication systems is traditionally generated at low frequency and subsequently multiplied using frequency multipliers, leading to a significant degradation of the LO noise floor at millimetre-wave frequencies. For this reason, the thesis considers low phase noise millimetre-wave signal source design optimised for future wideband millimetre-wave communications.In an oscillator, low frequency noise (LFN) is up-converted into phase noise around the microwave signal. Thus, aiming for low phase noise oscillator design, LFN characterisations and comparisons of several common III-V transistor technologies, e.g. GaAs-InGaP HBTs, GaAs pHEMTs, and GaN HEMTs, are carried out. It is shown that GaN HEMTs have good potential for oscillator applications where far-carrier phase noise performance is critical, e.g. wideband millimetre-wave communications. Since GaN HEMT is identified as an attractive technology for low noise floor oscillator applications, an in-depth study of some factors which affects LFN characteristics of III-N GaN HEMTs such as surface passivation methods and variations in transistor geometry are also investigated. It is found that the best surface passivation and deposition method can improve the LFN level of GaN HEMT devices significantly, resulting in a lower oscillator phase noise. Several MMIC GaN HEMT based oscillators including X-band Colpitts voltage-controlled-oscillators (VCOs) and Ka-band reflection type oscillators are demonstrated. It is verified that GaN HEMT based oscillators can reach a low noise floor. For instance, X-band GaN HEMT VCOs and a Ka-band GaN HEMT reflection type oscillator with 1 MHz phase noise performance of -135 dBc/Hz and -129 dBc/Hz, respectively, are demonstrated. These results are not only state-of-the-art for GaN HEMT oscillators, but also in-line with the best performance reported for GaAs-InGaP HBT based oscillators. Further, the MMIC oscillator designs are combined with accurate phase noise calculations based on a cyclostationary method and experimental LFN data. It has been seen that the measured and calculated phase noise agree well.The final part of this thesis covers low phase noise millimetre-wave signal source design and a comparison of different architectures and technological approaches. Specifically, a fundamental frequency 220 GHz oscillator is designed in advanced 130 nm InP DHBT process and a D-band signal source is based on the Ka-band GaN HEMT oscillator presented above and followed by a SiGe BiCMOS MMIC including a sixtupler and an amplifier. The Ka-band GaN HEMT oscillator is used to reach the critical low noise floor. The 220 GHz signal source presents an output power around 5 dBm, phase noise of -110 dBc/Hz at 10 MHz offset and a dc-to-RF efficiency in excess of 10% which is the highest number reported in open literature for a fundamental frequency signal source beyond 200 GHz. The D-band signal source, on the other hand, presents an output power of 5 dBm and phase noise of -128 dBc/Hz at 10 MHz offset from a 135 GHz carrier signal. Commenting on the performance of these two different millimetre-wave signal sources, the GaN HEMT/SiGe HBT source presents the best normalized phase noise at 10 MHz, while the integrated InP HBT oscillator demonstrates significantly better conversion efficiency and still a decent phase noise

Realization of a low noise amplifier using 0.35 um SiGe-BicMOS Technology for IEEE 802.11a applications /

The trend demand for towards interactive multimedia services has forced the development of new wireless systems that has greater bandwidths. The evolution of current wireless communication systems has been very rapid. The main goal has been small-size and low-cost transceivers that can be designed for different applications. Data communication systems in compliant with IEEE 802.11a wireless local area network (WLAN) standard has found widespread use, meeting the market demands, for the last few years. Next generation WLAN operates in the 5-6 GHz frequency range. A front-end receiver capable of operating within this frequency range is essential to meet the current and future of products. One of the critical components, allowing the common use of the technology can be attributed to the high performance Low Noise Amplifiers (LNA) in the receiver chain of the 802.11a transceivers. In IEEE 802.11a, there are three frequency bands; 5.15GHz - 5.25GHz, 5.25GHz - 5.35GHz and 5.725GHz - 5.825GHz. In this thesis, we designed and fabricated a single-stage cascode amplifier with emitter inductive degeneration using 0.35 ´m-SiGe BiCMOS process for IEEE 802.11a receivers. The electromagnetic (EM) simulations of the passive components are performed by using Agilent MOMENTUM® tool and all the parasitic components are extracted and compensated, a crucial step for optimizing the performance parameters of the LNA. The simulation results are very similar to measurement results, confirming the effectiveness of design methodology provided in this work