Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Dynamically Controllable Integrated Radiation and Self-Correcting Power Generation in mm-Wave Circuits and Systems

This thesis presents novel design methodologies for integrated radiators and power generation at mm-wave frequencies that are enabled by the continued integration of various electronic and electromagnetic (EM) structures onto the same substrate. Beginning with the observation that transistors and their connections to EM radiating structures on an integrated substrate are essentially free, the concept of multi-port driven (MPD) radiators is introduced, which opens a vast design space that has been generally ignored due to the cost structure associated with discrete components that favors fewer transistors connected to antennas through a single port. From Maxwell's equations, a new antenna architecture, the radial MPD antennas based on the concept of MPD radiators, is analyzed to gain intuition as to the important design parameters that explain the wide-band nature of the antenna itself. The radiator is then designed and implemented at 160 GHz in a 0.13 um SiGe BiCMOS process, and the single element design has a measured effective isotropic radiated power (EIRP) of +4.6 dBm with a total radiated power of 0.63 mW. Next, the radial MPD radiator is adapted to enable dynamic polarization control (DPC). A DPC antenna is capable of controlling its radiated polarization dynamically, and entirely electronically, with no mechanical reconfiguration required. This can be done by having multiple antennas with different polarizations, or within a single antenna that has multiple drive points, as in the case of the MPD radiator with DPC. This radiator changes its polarization by adjusting the relative phase and amplitude of its multiple ports to produce polarizations with any polarization angle, and a wide range of axial ratios. A 2x1 MPD radiator array with DPC at 105 GHz is presented whose measurements show control of the polarization angle throughout the entire 0 degree through 180 degree range while in the linear polarization mode and maintaining axial ratios above 10 dB in all cases. Control of the axial ratio is also demonstrated with a measured range from 2.4 dB through 14 dB, while maintaining a fixed polarization angle. The radiator itself has a measured maximum EIRP of +7.8 dBm, with a total radiated power of 0.9 mW, and is capable of beam steering. MPD radiators were also applied in the domain of integrated silicon photonics. For these designs, the driver transistor circuitry was replaced with silicon optical waveguides and photodiodes to produce a 350 GHz signal. Three of these optical MPD radiator designs have been implemented as 2x2 arrays at 350 GHz. The first is a beam forming array that has a simulated gain of 12.1 dBi with a simulated EIRP of -2 dBm. The second has the same simulated performance, but includes optical phase modulators that enable two-dimensional beam steering. Finally, a third design incorporates multi-antenna DPC by combining the outputs of both left and right handed circularly polarized MPD antennas to produce a linear polarization with controllable polarization angle, and has a simulated gain of 11.9 dBi and EIRP of -3 dBm. In simulation, it can tune the polarization from 0 degrees through 180 degrees while maintaining a radiated power that has a 0.35 dB maximum deviation from the mean. The reliability of mm-wave radiators and power amplifiers was also investigated, and two self-healing systems have been proposed. Self-healing is a global feedback method where integrated sensors detect the performance of the circuit after fabrication and report that data to a digital control algorithm. The algorithm then is capable of setting actuators that can control the performance of the mm-wave circuit and counteract any performance degradation that is observed by the sensors. The first system is for a MPD radiator array with a partially integrated self-healing system. The self-healing MPD radiator senses substrate modes through substrate mode pickup sensors and infers the far-field radiated pattern from those sensors. DC current sensors are also included to determine the DC power consumption of the system. Actuators are implemented in the form of phase and amplitude control of the multiple drive points. The second self-healing system is a fully integrated self-healing power amplifier (PA) at 28 GHz. This system measures the output power, gain and efficiency of the PA using radio frequency (RF) power sensors, DC current sensors and junction temperature sensors. The digital block is synthesized from VHDL code on-chip and it can actuate the output power combining matching network using tunable transmission line stubs, as well as the DC operating point of the amplifying transistors through bias control. Measurements of 20 chips confirm self-healing for two different algorithms for process variation and transistor mismatch, while measurements from 10 chips show healing for load impedance mismatch, and linearity healing. Laser induced partial and total transistor failure show the benefit of self-healing in the case of catastrophic failure, with improvements of up to 3.9 dB over the default case. An exemplary yield specification shows self-healing improving the yield from 0% up through 80%.</p

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Realization of a voltage controlled oscillator using 0.35 um sige-bicmos technology for multi-band applications

The stable growth in wireless communications market has engendered the interoperability of various standards in a single broadband frequency range from hundred MHz up to several GHz. This frequency range consists of various wireless applications such as GSM, Bluetooth and WLAN. Therefore, an agile wireless system needs smart RF front-ends for functioning properly in such a crowded spectrum. As a result, the demand for multi-standard RF transceivers which put various wireless and cordless phone standards together in one structure was increased. The demand for multi-standard RF transceivers gives a key role to reconfigurable wideband VCO operation with low-power and low-phase noise characteristics. Besides agility and intelligence, such a communication system (GSM, WLAN, Global Positioning Systems, etc. ) required meeting the requirements of several standards in a cost-effective way. This, when cost and integration are the major concerns, leads to the exploitation of Si-based technologies. In this thesis, an integrated 2.2-5.7GHz Multi-band differential LC VCO for Multi-standard Wireless Communication systems was designed utilizing 0.35μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78GHz, 3.22-3.53GHz, 3.48-3.91GHz and 4.528-5.7GHz) with a maximum bandwidth of 1.36GHz and a minimum bandwidth of 300MHz. The designed and simulated VCO can generate a differential output power between 0.992 dBm and -6.087 dBm with an average power consumption of 44.21mW including the buffers. The average second and third harmonics level were obtained as -37.21 dBm and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment

Analysis and Design of Radio Frequency Integrated Circuits for Breast Cancer Radar Imaging in CMOS Technology

Breast cancer is by far the most incident tumor among female population. Early stage prevention is a key factor in delivering long term survival of breast cancer patients. X-ray mammography is the most commonly used diagnostic technique to detect non-palpable tumors. However, 10-30% of tumors are missed by mammography and ionizing radiations together with breast compression do not lead to comfort in patient treatment. In this context, ultrawideband microwave radar technology is an attractive alternative. It relies on the dielectric contrast of normal and malignant tissues at microwave frequencies to detect and locate tumors inside the breast. This work presents the analysis and design of radio frequency integrated circuits for breast cancer imaging in CMOS technology. The first part of the thesis concerns the system analysis. A behavioral model of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system are presented. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used to on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. Insight is given into I/Q phase inaccuracies and their impact on the quality of the final reconstructed images. The result is that the simplicity of the direct conversion architecture makes the receiver more robust toward the critical impairments for this application. The second part of the thesis is dedicated to the circuit design. The main achievement is a 65nm CMOS 2-16GHz stepped frequency radar transceiver for medical imaging. The RX features 36dB conversion gain, >29dBm compression point, 7dB noise figure, and 30Hz 1/f noise corner. The TX outputs 14dBm with >40dBc harmonic rejection and <109dBc/Hz phase noise at 1MHz offset. Overall power dissipation is 204mW from 1.2V supply. The radar achieves 3mm resolution within the body, and 107dB dynamic range, a performance enabling the use for breast cancer diagnostic imaging. To further assess the capabilities of the proposed radar, a physical breast phantom was synthesized and two targets mimicking two tumors were buried inside the breast. The targets are clearly identified and correctly located, effectively proving the performance of the designed radar as a possible tool for breast cancer detection

Gravitational Wave Detection and Low-Noise Sapphire Oscillators

This thesis describes the development of an ultra-low noise sapphire resonator oscillator that is tunable over X-band. While undertaking this task the author has explained some interesting and very useful phenomena in regards to the design and understanding of multi-mode resonant cavities and oscillators. The oscillator was constructed to operate as the pump oscillator in the superconducting parametric transducer system, attached to a 1.5-tonne niobium resonant bar gravitational wave detector. The effects of incorporating the pump oscillator with the parametric transducer and resonant bar system are analyzed to enable prediction of the detector sensitivity. The detector was the first massive precision optomechanical system ever built. With the resurgence in interest in resonant detectors, this thesis has important work on multi-mode acoustic systems, coupled to a highly sensitive parametric transducer relevant for many fields of research today.Comment: PhD Thesis, University of Western Australi

CMOS ASIC Design of Multi-frequency Multi-constellation GNSS Front-ends

With the emergence of the new global navigation satellite systems (GNSSs) such as Galileo, COMPASS and GLONASS, the US Global Positioning System (GPS) has new competitors. This multiplicity of constellations will offer new services and a much better satellite coverage. Public regulated service (PRS) is one of these new services that Galileo, the first global positioning service under civilian control, will offers. The PRS is a proprietary encrypted navigation designed to be more reliable and robust against jamming and provides premium quality in terms of position and timing and continuity of service, but it requires the use of FEs with extended capabilities. The project that this thesis starts from, aims to develop a dual frequency (E1 and E6) PRS receiver with a focus on a solution for professional applications that combines affordability and robustness. To limit the production cost, the choice of a monolithic design in a multi-purpose 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology have been selected, and to reduce the susceptibility to interference, the targeted receiver is composed of two independent FEs. The first ASIC described here is such FEs bundle. Each FE is composed of a radio frequency (RF) chain that includes a low-noise amplifier (LNA), a quadrature mixer, a frequency synthesizer (FS), two intermediate frequency (IF) filters, two variable-gain amplifiers (VGAs) and two 6-bit flash analog-to-digital converters (ADCs). Each have an IF bandwidth of 50 MHz to accommodate the wide-band PRS signals. The FE achieves a 30 dB of dynamic gain control at each channel. The complete receivers occupies a die area of 11.5 mm2 while consuming 115 mW from a supply of a 1.8 V. The second ASIC that targets civilian applications, is a reconfigurable single-channel FE that permits to exploit the interoperability among GNSSs. The FE can operate in two modes: a ¿narrow-band mode¿, dedicated to Beidou-B1 with an IF bandwidth of 8 MHz, and a ¿wide-band mode¿ with an IF bandwidth of 23 MHz, which can accommodate simultaneous reception of Beidou-B1/GPS-L1/Galileo-E1. These two modes consumes respectively 22.85 mA and 28.45 mA from a 1.8 V supply. Developed with the best linearity in mind, the FE shows very good linearity with an input-referred 1 dB compression point (IP1dB) of better than -27.6 dBm. The FE gain is stepwise flexible from 39 dB and to a maximum of 58 dB. The complete FE occupies a die area of only 2.6 mm2 in a 0.18 µm CMOS. To also accommodate the wide-band PRS signals in the IF section of the FE, a highly selective wide-tuning-range 4th-order Gm-C elliptic low-pass filter is used. It features an innovative continuous tuning circuit that adjusts the bias current of the Gm cell¿s input stage to control the cutoff frequency. With this circuit, the power consumption is proportional to the cutoff frequency thus the power efficiency is achieved while keeping the linearity near constant. Thanks to a Gm switching technique, which permit to keep the signal path switchless, the filter shows an extended tuning of the cutoff frequency that covers continuously a range from 7.4 MHz to 27.4 MHz. Moreover the abrupt roll-off of up to 66 dB/octave, can mitigate out-of-band interference. The filter consumes 2.1 mA and 7.5 mA at its lowest and highest cutoff frequencies respectively, and its active area occupies, 0.23 mm2. It achieves a high input-referred third-order intercept point (IIP3) of up to -1.3 dBVRMS