Gray-code TDC with improved linearity and scalability for LiDAR applications

This paper presents a TDC architecture based on a gray code oscillator with improved linearity, for FPGA implementations. The proposed architecture introduces manual routing as a method to improve the TDC linearity and precision, by controlling the gray code oscillator Datapath, which also reduces the need for calibration mechanisms. Furthermore, the proposed manual routing procedure improves the performance homogeneity across multiple TDC channels, enabling the use of the same calibration module across multiple channels, if further improved precision is required. The proposed TDC channel uses only 16 FPGA logic resources (considering the Xilinx 7 series platform), making it suitable for applications where a large number of measurement channels are required. To validate the proposed architecture and routing procedure, two channels were integrated with a coarse counter, a FIFO memory and an AXI interface, to assemble the pulse measurement unit. A comparison between the default routing implementation and the proposed manual routing has been performed, shown an improvement of 27% on the overall TDC single-shot precision. The implemented TDC achieved a 380 ps RMS resolution, a maximum DNL of 0.38 LSB and a peak-to-peak INL of 0.69 LSB, corresponding to a 21.7% and 70.4% improvement, respectively, when compared to the default design approach.FCT - Fundação para a Ciência e a Tecnologia(037902

The BrightEyes-TTM: an open-source time-tagging module for fluorescence lifetime imaging microscopy applications

The aim of this Ph.D. work is to reason and show how an open-source multi-channel and standalone time-tagging device was developed, validated and used in combination with a new generation of single-photon array detectors to pursue super-resolved time-resolved fluorescence lifetime imaging measurements. Within the compound of time-resolved fluorescence laser scanning microscopy (LSM) techniques, fluorescence lifetime imaging microscopy (FLIM) plays a relevant role in the life-sciences field, thanks to its ability of detecting functional changes within the cellular micro-environment. The recent advancements in photon detection technologies, such as the introduction of asynchronous read-out single-photon avalanche diode (SPAD) array detectors, allow to image a fluorescent sample with spatial resolution below the diffraction limit, at the same time, yield the possibility of accessing the single-photon information content allowing for time-resolved FLIM measurements. Thus, super-resolved FLIM experiments can be accomplished using SPAD array detectors in combination with pulsed laser sources and special data acquisition systems (DAQs), capable of handling a multiplicity of inputs and dealing with the single-photons readouts generated by SPAD array detectors. Nowadays, the commercial market lacks a true standalone, multi-channel, single-board, time-tagging and affordable DAQ device specifically designed for super-resolved FLIM experiments. Moreover, in the scientific community, no-efforts have been placed yet in building a device that can compensate such absence. That is why, within this Ph.D. project, an open-source and low-cost device, the so-called BrightEyes-TTM (time tagging module), was developed and validated both for fluorescence lifetime and time-resolved measurements in general. The BrightEyes-TTM belongs to a niche of DAQ devices called time-to-digital converters (TDCs). The field-gate programmable array (FPGA) technology was chosen for implementing the BrightEyes-TTM thanks to its reprogrammability and low cost features. The literature reports several different FPGA-based TDC architectures. Particularly, the differential delay-line TDC architecture turned out to be the most suitable for this Ph.D. project as it offers an optimal trade-off between temporal precision, temporal range, temporal resolution, dead-time, linearity, and FPGA resources, which are all crucial characteristics for a TDC device. The goal of the project of pursuing a cost-effective and further-upgradable open-source time-tagging device was achieved as the BrigthEyes-TTM was developed and assembled using low-cost commercially available electronic development kits, thus allowing for the architecture to be easily reproduced. BrightEyes-TTM was deployed on a FPGA development board which was equipped with a USB 3.0 chip for communicating with a host-processing unit and a multi-input/output custom-built interface card for interconnecting the TTM with the outside world. Licence-free softwares were used for acquiring, reconstructing and analyzing the BrightEyes-TTM time-resolved data. In order to characterize the BrightEyes-TTM performances and, at the same time, validate the developed multi-channel TDC architecture, the TTM was firstly tested on a bench and then integrated into a fluorescent LSM system. Yielding a 30 ps single-shot precision and linearity performances that allows to be employed for actual FLIM measurements, the BrightEyes-TTM, which also proved to acquire data from many channels in parallel, was ultimately used with a SPAD array detector to perform fluorescence imaging and spectroscopy on biological systems. As output of the Ph.D. work, the BrightEyes-TTM was released on GitHub as a fully open-source project with two aims. The principal aim is to give to any microscopy and life science laboratory the possibility to implement and further develop single-photon-based time-resolved microscopy techniques. The second aim is to trigger the interest of the microscopy community, and establish the BrigthEyes-TTM as a new standard for single-photon FLSM and FLIM experiments

A novel synchronizer for a 17.9ps Nutt Time-to-Digital Converter implemented on FPGA

The evolution of Field-Programmable Gate Array (FPGA) technology triggered the appearance of FPGAs with higher operating frequencies and large number of resources. Simultaneously, the evolution of the FPGAs design tools has simplified the development process, reducing the time to market. These factors made FPGA platforms attractive for several applications, including time-of-flight applications that require the implementation of Time-to-Digital Converters (TDC). This work presents a Nutt TDC, based on a coarse counter and a Tapped Delay Line, with 17.9 picoseconds resolution and 5.4 LSB differential nonlinearity (DNL), implemented in a Xilinx Zynq-7000 FPGA, to be used on LiDAR applications and pull-in time measuring in MEMS accelerometers systems.This work was supported by a Portuguese Scholarship from FCT - Fundação para a Ciência e Tecnologia and Bosch Car Multimedia, under the Advanced Engineering Systems for Industry (AESI) doctoral program. (Scholarship ID: PDE/BDE/114562/2016) and COMPETE and FCT: POCI- 01-0145-FEDER-007043 within the Project Scope: UID/CEC/00319/201

FPGA를 이용한 시간 기반 고집적 PET 데이터 수집 장치

학위논문(박사)--서울대학교 대학원 :의과대학 의과학과,2019. 8. 이재성.Positron emission tomography (PET) is a widely used functional imaging device for diagnosing cancer and neurodegenerative diseases. PET instrumentation studies focus on improving both spatial resolution and sensitivity to improve the lesion detectability while reducing radiation exposure to patients. The silicon photomultiplier (SiPM) is a photosensor suitable for high-performance PET scanners owing to its compact size and fast response. However, the SiPM-based PET scanners require a large number of readout channels owing to a high level of granularity. For example, the typical whole-body PET scanners require more than 40,000 SiPM channels. Therefore, the highly integrated data acquisition (DAQ) system that can digitize a large number of SiPM signal with preserving its fast temporal response is required to develop the high-performance SiPM-based PET scanners. Time-based signal digitization is a promising method to develop highly integrated DAQ systems owing to its simple circuitry and fast temporal response. In this thesis, studies on developing highly integrated DAQ systems using a field-programmable gate array (FPGA) were presented. Firstly, a 10-ps time-to-digital converter (TDC) implemented within the FPGA was developed. The FPGA-TDCs suffer from the non-linearity, because FPGAs are not originally designed to implement TDC. We proposed the dual-phase sampling architecture considering the FPGA clock distribution network to mitigate the TDC non-linearity. In addition, we developed the on-the-fly calibrator that compensated the innate bin width variations without introducing the dead time. Secondly, the time-based SiPM multiplexing and readout method was developed using the principle of the global positioning system (GPS). The signal traces connecting every SiPM to four timing channels were used to encode the position information. The position information was obtained using the innate transit time differences measured by four FPGA-TDCs. In addition, the minimal signal distortion by multiplexing circuit allowed to use a time-over-threshold (ToT) method for energy measurement after multiplexing. Thirdly, we proposed a new FPGA-only digitizer. The programmable FPGA input/output (I/O) port was configured with stub-series terminated logic (SSTL) input receiver, and each FPGA I/O port functioned as a high-performance voltage comparator with a fast temporal response. We demonstrated that the FPGA can be used as a high-performance DAQ system by directly digitizing the time-of-flight (TOF) PET detector signals using the FPGA without any front-end electronics. Lastly, we developed comparator-less charge-to-time converter (QTC) DAQ systems to collect data from a prototype high-resolution brain PET scanner. The energy channel consisted of a QTC combined with the SSTL input receiver of the FPGA. The timing channel was a TDC implemented within the same FPGA. The detailed structure of brain phantom was well-resolved using the developed high-resolution brain PET scanner and the highly-integrated time-based DAQ systems.양전자방출단층촬영 (Positron Emission Tomography; PET) 장치는 암과 신경퇴행성 질환을 영상화하는 데 널리 쓰이는 기능 영상장치이다. 최근 PET 스캐너 연구는 공간 분해능과 장비 민감도를 높여 병변의 진단을 쉽게 하면서 환자의 방사선 피폭을 줄이는 방법에 초점을 맞추고 있다. 실리콘 관증배기 (silicon photomultiplier; SiPM)은 크기가 작고 반응속도가 빠르기 때문에 고성능 PET 스캐너에 적합한 광검출소자이다. 하지만 SiPM 기반 PET 스캐너는 개별 SiPM의 크기가 작기 때문에 수많은 데이터 수집 채널이 필요하다. 예를 들어, 전신 PET 스캐너를 SiPM으로 구성할 경우 40,000개 이상의 SiPM 소자가 필요하다. 따라서, SiPM의 성능을 유지하면서 다채널 신호 디지털화가 가능한 고집적 데이터 수집장치 (data acquisition; DAQ)가 고성능 SiPM PET 스캐너 개발에 필요하다. 시간 기반 신호 디지털 방법은 단순한 회로와 빠른 반응속도 덕분에 고집적 DAQ 시스템을 구현하는 유망한 방법이다. 본 학위논문에서는 프로그램 가능 게이트 배열 (field-programmable gate array; FPGA)을 이용하여 고집적 DAQ 시스템을 개발하는 연구내용을 다룬다. 첫째로, 10 ps 의 분해능을 갖는 FPGA 기반 시간-디지털 변환기 (time-to-digital converter; TDC)를 개발하였다. FPGA는 TDC 구현을 위한 집적소자가 아니므로 FPGA에 구현된 TDC는 일반적으로 비선형성 문제를 가진다. 이를 해결하기 위해 비선형성 문제를 야기하는 FPGA의 클락 신호 분배 구조를 고려하여 이중 위상 샘플링 방법을 제안하였다. 또한, FPGA TDC 고유의 불균일한 분해능을 측정하고 보상하기 위하여 실시간 보정기술을 개발하였다. 둘째로, GPS 원리를 사용한 시간 기반 신호 부호화 (multiplexing) 및 수집 방법을 개발하였다. 부호화 회로는 SiPM을 네 개의 시간 수집 채널로 연결한 도선으로 구성되고 위치정보는 각 SiPM으로부터 네 개의 시간 수집 채널까지의 고유한 도파시간 차이를 계산해서 수집할 수 있다. 또한, 기존 전하 분배 부호화 회로와 달리 신호가 왜곡되지 않기 때문에 문턱 전압 방법 (time-over-threshold; ToT) 방식으로 에너지를 수집하는 것이 가능하였다. 셋째로, FPGA만으로 아날로그 신호를 디지털화 하는 새로운 방법을 개발하였다. FPGA의 프로그램 가능 입출력포트를 stub-series terminated logic (SSTL) 수신기로 프로그램하면, 각각의 FPGA 입출력포트가 빠른 시간 반응성을 가진 고성능 전압비교기로 동작한다. 비정시간 (time-of-flight; TOF) 측정 가능 PET 검출기의 신호를 전단회로 없이 FPGA만으로 디지털화하여 FPGA를 고성능 DAQ 장치로 사용할 수 있음을 입증하였다. 마지막으로, 공간분해능이 뛰어난 뇌전용 스캐너로부터 데이터를 수집하기 위해 전압비교기를 사용하지 않는 시간 기반 DAQ 장치를 개발하였다. 에너지 측정 채널은 시간-전하 변환기 (charge-to-time converter; QTC)와 FPGA의 SSTL 수신기로 구성하였다. 시각 측정 채널은 FPGA 기반 TDC로 구성하였다. 개발한 뇌전용 스캐너와 고집적 시간 기반 DAQ 장치로 획득한 뇌모양 팬텀의 자세한 구조들은 잘 구분되었다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Positron Emission Tomography 1 1.1.2. Silicon Photomultiplier 1 1.1.3. Data Acquisition System 2 1.1.4. Time-based Signal Digitization Method 3 1.2. Purpose of Research 6 Chapter 2. FPGA-based Time-to-Digital Converter 8 2.1. Background 8 2.2. Materials and Methods 9 2.2.1. Tapped-Delay-Line TDC 9 2.2.2. FPGA 11 2.2.3. Dual-Phase TDL TDC with On-the-Fly Calibrator 11 2.2.3.1. FPGA Clock Distribution Network 11 2.2.3.2. The Principle of Dual-Phase TDL TDC 14 2.2.3.3. The Principle of Pipelined On-the-Fly Calibrator 16 2.2.3.4. Implementation of Dual-Phase TDL TDC with On-the-Fly Calibrator 18 2.2.4. Experimental Setups and Data Processing 20 2.2.4.1. TDC Characteristics 21 2.2.4.2. Arrival Time Difference Measurements 22 2.3. Results 24 2.3.1. TDC Characteristics 24 2.3.2. Arrival Time Difference Measurements 25 2.4. Discussion 28 Chapter 3. Time-based Multiplexing Method 29 3.1. Background 29 3.2. Materials and Methods 30 3.2.1. Delay Grid Multiplexing 30 3.2.2. Detector for Concept Verification 32 3.2.3. Front-end Electronics 34 3.2.4. Experimental Setups 35 3.2.4.1. Data Acquisition Using the Waveform Digitizer 37 3.2.4.2. Data Acquisition Using the FPGA-TDC 37 3.2.5. Data Processing and Analysis 38 3.2.5.1. Waveform Digitizer 38 3.2.5.2. FPGA-TDC 41 3.3. Results 44 3.3.1. Waveform Digitizer 44 3.3.1.1. Waveform, Rise Time, and Decay Time 44 3.3.1.2. Flood Map 46 3.3.1.3. Energy 48 3.3.1.4. CTR 49 3.3.2. FPGA-TDC 50 3.3.2.1. ToT and Energy 50 3.3.2.2. Flood Map 51 3.3.2.3. CTR 52 3.4. Discussion 53 Chapter 4. FPGA-Only Signal Digitization Method 54 4.1. Background 54 4.2. Materials and Methods 56 4.2.1. Single-ended Memory Interface Input Receiver 56 4.2.2. SeMI Digitizer 56 4.2.3. Experimental Setup for Intrinsic Performance Characterization 59 4.2.3.1. ToT 59 4.2.3.2. Timing 60 4.2.4. Experimental Setup for Individual Signal Digitization 60 4.2.4.1. TOF PET Detector 60 4.2.4.2. Data Acquisition Using the Waveform Digitizer 61 4.2.4.3. Data Acquisition Using the SeMI Digitizer 63 4.2.4.4. Data Analysis 63 4.3. Results 64 4.3.1. Results of Intrinsic Performance Characterization 64 4.3.1.1. ToT 64 4.3.1.2. Timing 65 4.3.2. Results of Individual Signal Digitization 66 4.3.2.1. Energy 66 4.3.2.2. CTR 67 4.4. Discussion 68 Chapter 5. Comparator-less QTC DAQ Systems for High-Resolution Brain PET Scanners 70 5.1. Background 70 5.2. Materials and Methods 72 5.2.1. Brain PET Scanner 72 5.2.1.1. Block Detector 72 5.2.1.2. Sector 73 5.2.1.3. Scanner Geometry 74 5.2.2. Comparator-less QTC DAQ System 75 5.2.3. Data Acquisition Chain of Brain PET Scanner 79 5.2.4. Experimental Setups and Data Processing 79 5.2.4.1. Energy Linearity 79 5.2.4.2. Performance Evaluation of Block Detector 80 5.2.4.3. Phantom Studies 82 5.3. Results 83 5.3.1. Energy Linearity 83 5.3.2. Performance Evaluation of Block Detector 83 5.3.3. Phantom Studies 85 5.4. Discussion 87 Chapter 6. Conclusions 89 Bibliography 90 Abstract in Korean (국문 초록) 94Docto

Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays

Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required

Efficient time-to-digital converters in 20 nm FPGAs with wave union methods

The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, a famous earlier study concluded that the WU method is not suitable for UltraScale field-programmable gate array (FPGA) devices, due to more severe bubble errors. This paper proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new sub-tapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDC combining the dual sampling (DS) structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square (RMS) resolution. Compared with previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs