PLUG-AND-PLAY TRANSCEIVER WITH HIGH GAIN AND ULTRA LOW NOISE FIGURE FOR IEEE 802.15.4 APPLICATION

This paper shows the design and performance simulation of a 2.4 GHz plug-and-play transceiver based on a high speed switch for IEEE 802.15.4 applications. The electrical design was optimized taking into account the scattering parameters, input-output impedance matching and minimum trace width. The simulation results show an important performance regarding the Noise Figure (0.38 dB) and gain (21 dB) at particular temperature for reception mode, transmission scattering parameters (S12 and S21) and reflection scattering parameters (all the rest parameters) for both mode operation (Power Amplifier and Low Noise Amplifier)

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation

A single propagation path multimode CMOS power amplifier based on the stacked topology

Orientador: Bernardo Rego Barros de Almeida LeiteCoorientador: André Augusto MarianoTese (doutorado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa : Curitiba, 28/06/2021Inclui referências: p. 54-56Resumo: Esta tese apresenta o projeto de um amplificador de potências (PA) prova-de-conceito com quatro perfis de eficiência de um caminho único de propagação, realizado com tecnologia CMOS 130 nm e operando em 2,4 GHz. Esse circuito se baseia em dois conceitos: na seleção da região de operação de transistores (triodo ou saturação) e na alteração da tensão de alimentação de uma arquitetura empilhada modificada. Nos modos de alta e baixa potência (todos transistores em saturação e um transistor em saturação e três em triodo, respectivamente), o ponto de compressão de 1 dB referenciado à saída (OCP1dB) e a eficiência adicionada à potência (PAE) no OCP1dB resultantes de simulação pós-layout são de 19,9 dBm e 25,7%; de 15,1 dBm e 20,5%, respectivamente. Para validar a operação desse PA, quatro tipos de sinais do padrão IEEE 802.11ax foram testados. Para sinais menos complexos (16 QAM) o PA pode operar sem que a ultrapasse os limites impostos pela máscara do padrão até uma potencia de saída (pout) de 17,8 dBm; para sinais mais complexos (1024 QAM) o PA pode operar até uma pout de 8,5 dBm. Por um lado, o circuito apresentado é capaz de ocupar uma pequena área, o que é uma vantagem em processos escaláveis, tais como o CMOS. Por outro lado, a complexidade de design é elevada, tendo em vista que a otimização de eficiência e potência é também função da interação entre os modos de operação.Abstract: This thesis presents the design of a proof-of-concept single propagation path four-mode power amplifier (PA) in 130 nm CMOS operating at 2.4 GHz. It is based on two concepts: the selection of the transistor's operation region (triode or saturation) and on the scaling of supply voltage of a modified stacked architecture. In high and low power modes (all transistors in saturation and one transistor in saturation and three in triode, respectively), the output-referred 1 dB compression point (OCP1dB) and the power added efficiency (PAE) in OCP1dB post-layout simulation results are 19.9 dBm and 25.7%; 15.1 dBm and 20.5%, respectively. To validate this PA's operation capability, four types of IEEE 802.11ax signals were tested. For less complex signals (16 QAM) the PA can operate without exceeding the limits imposed by the standard's mask up to an output power (pout) of 17.8 dBm; for more complex signals (1024 QAM) the PA can operate up to a pout of 8.5 dBm. On the one hand, the proposed circuit is capable of occupying a small area, which is an advantage in scalable processes, such as CMOS is. On the other hand, its design is complex, as optimization of efficiency and power is also a function of the interaction among operation modes

Adaptive Power Amplifiers for Modern Communication Systems with Diverse Operating Conditions

In this thesis, novel designs for adaptive power amplifiers, capable of maintaining excellent performance at dissimilar signal parameters, are presented. These designs result in electronically reconfigurable, single-ended and Doherty power amplifiers (DPA) that efficiently sustain functionality at different driving signal levels, highly varying time domain characteristics and wide-spread frequency bands. The foregoing three contexts represent those dictated by the diverse standards of modern communication systems. Firstly, two prototypes for a harmonically-tuned reconfigurable matching network using discrete radio frequency (RF) microelectromechanical systems (MEMS) switches and semiconductor varactors will be introduced. Following that is an explanation of how the varactor-based matching network was used to develop a high performance reconfigurable Class F-1 power amplifier. Afterwards, a systematic design procedure for realizing an electronically reconfigurable DPA capable of operating at arbitrary centre frequencies, average power levels and back-off efficiency enhancement power ranges is presented. Complete sets of closed-form equations are outlined which were used to build tunable matching networks that compensate for the deviation of the Doherty distributed elements under the desired deployment scenarios. Off-the-shelf RF MEMS switches are used to realize the reconfigurability of the adaptive Doherty amplifiers. Finally, based on the derived closed-form equations, a tri-band, monolithically integrated DPA was realized using the Canadian Photonics Fabrication Centre (CPFC®) GaN500 monolithic microwave integrated circuit (MMIC) process. Successful integration of high power, high performance RF MEMS switches within the MMIC process paved the way for the realization of the frequency-agile, integrated version of the adaptive Doherty amplifier

Electronically reconfigurable wideband high-power amplifier architecture for modern RF systems (LMBA)

As mobile communications and other microwave systems continue to evolve designers and system architects are pushing for ever increasing bandwidth as multiple RF systems are increasingly sharing a common front-end amplifier to save space and reduce routing complexity and losses associated with having separate amplifier systems. The power amplifier in many RF systems typically accounts for the majority of the power consumption of the device or transmitter platform, it is therefore paramount that to improve the efficiency of these systems RFPA designs must be tailored to achieve the highest possible efficiency. RFPA modes of operation and architectures to achieve higher efficiency have been developed, but often come with compromises to other system aspects such as linearity, control complexity and most commonly bandwidth. With the next generation 5G communications specification including frequency bands of up to the Ka frequency spectrum and the high capacity multi-octave spectrum bands allocated at L-C band, traditional RFPA efficiency enhancement techniques struggle to be implementable due to either the high frequency requirements of the control systems needed or due to the bandwidth restrictions of such techniques. II Conventionally narrow bandwidth X-band radar systems that used to be operated at saturated output power conditions are starting to explore multimode operation that require more power back-off (PBO) and control of the RFPA, so are searching for techniques that are applicable at X-band and can achieve the same level of PBO requirements demanded by modern communication modulation standards while working to the power and cooling restraints that come from a limited application platform such as fighter aircraft. Similarly, such fighter platforms are demanding increased electronic warfare (EW) capability which are restrained to the same platform limitations but often need to cover multi-octave bandwidths where traditional efficiency enhancement techniques cannot be applied. This research will focus on wideband efficiency enhancement for both saturated and PBO scenarios that present a frequency agnostic technique of overcoming conventional limitations. The novel work presented is based around the quintessential, but relatively old, bandwidth extension architecture known as the balanced amplifier. The addition of a secondary control signal has been proposed whereby the operating impedance of the amplifier can be dramatically modulated while maintaining the fundamental advantage the balanced amplifier allow, that is multi-octave bandwidth. III The power of this architecture can draw similarities in impedance control afforded by load pull systems, in particular active load-pull. With the correct control signal, any impedance is able to be presented to the transistors to keep them operating at maximum efficiency, where passive matching alone is not able to achieve such efficiency due to fundamental matching theory. Due to the active element of this novel architecture, named the Load Modulated Balanced Amplifier (LMBA), frequency restrictive and thus band limiting elements present in other efficiency enhancement techniques; such as the quarter wave inverter present in the Doherty Amplifier or the difficulty of realizing the modulator in Envelope Tracking (ET) are not present. This thesis will present the fundamental theory driving the operation of an LMBA along with multiple implementations, each targeted at differing applications and different frequency bands to demonstrate the versatility and frequency independence of the technique

Electronically reconfigurable wideband high-power amplifier architecture for modern RF systems (LMBA)

As mobile communications and other microwave systems continue to evolve designers and system architects are pushing for ever increasing bandwidth as multiple RF systems are increasingly sharing a common front-end amplifier to save space and reduce routing complexity and losses associated with having separate amplifier systems. The power amplifier in many RF systems typically accounts for the majority of the power consumption of the device or transmitter platform, it is therefore paramount that to improve the efficiency of these systems RFPA designs must be tailored to achieve the highest possible efficiency. RFPA modes of operation and architectures to achieve higher efficiency have been developed, but often come with compromises to other system aspects such as linearity, control complexity and most commonly bandwidth. With the next generation 5G communications specification including frequency bands of up to the Ka frequency spectrum and the high capacity multi-octave spectrum bands allocated at L-C band, traditional RFPA efficiency enhancement techniques struggle to be implementable due to either the high frequency requirements of the control systems needed or due to the bandwidth restrictions of such techniques. II Conventionally narrow bandwidth X-band radar systems that used to be operated at saturated output power conditions are starting to explore multimode operation that require more power back-off (PBO) and control of the RFPA, so are searching for techniques that are applicable at X-band and can achieve the same level of PBO requirements demanded by modern communication modulation standards while working to the power and cooling restraints that come from a limited application platform such as fighter aircraft. Similarly, such fighter platforms are demanding increased electronic warfare (EW) capability which are restrained to the same platform limitations but often need to cover multi-octave bandwidths where traditional efficiency enhancement techniques cannot be applied. This research will focus on wideband efficiency enhancement for both saturated and PBO scenarios that present a frequency agnostic technique of overcoming conventional limitations. The novel work presented is based around the quintessential, but relatively old, bandwidth extension architecture known as the balanced amplifier. The addition of a secondary control signal has been proposed whereby the operating impedance of the amplifier can be dramatically modulated while maintaining the fundamental advantage the balanced amplifier allow, that is multi-octave bandwidth. III The power of this architecture can draw similarities in impedance control afforded by load pull systems, in particular active load-pull. With the correct control signal, any impedance is able to be presented to the transistors to keep them operating at maximum efficiency, where passive matching alone is not able to achieve such efficiency due to fundamental matching theory. Due to the active element of this novel architecture, named the Load Modulated Balanced Amplifier (LMBA), frequency restrictive and thus band limiting elements present in other efficiency enhancement techniques; such as the quarter wave inverter present in the Doherty Amplifier or the difficulty of realizing the modulator in Envelope Tracking (ET) are not present. This thesis will present the fundamental theory driving the operation of an LMBA along with multiple implementations, each targeted at differing applications and different frequency bands to demonstrate the versatility and frequency independence of the technique

Analysis and Design of CMOS Radio-Frequency Power Amplifiers

The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources