A 2.4 GHz CMOS class-F power amplifier with reconfigurable load-impedance matching

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output matching at fundamental frequency without affecting the class-F harmonic tuning up to 3rd harmonic. To the best of our knowledge, this is the first design of a CMOS class-F PA addressed to compensate the effect of load variation. Measurement results for 50 ohm load impedance show a maximum PAE of 26% and maximum output power of 19.2 dBm. The measured total harmonic distortion is 4.9%. Measurement results for load values other than 50 ohm show that PAE increases from 6.5% (not-tuned PA) up to 19.9% (tuned PA) with the same output power (19.2 dBm). Tuning also reduces the adjacent-channel leakage ratio by 5 dB and the spectral regrowth of a Wi-Fi signal at the PA output. The size of the fabricated chip is 1.6 mm × 1.6 mm.Peer ReviewedPostprint (author's final draft

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS

Next generation wireless communication technology requires mobile devices and base stations to support multiband multimode frequencies with higher data rate because of the type of enriched and enhanced features and services that are provided to the end user. The challenge for next generation PA designers is to provide high efficiency, output power and good linearity across multiple frequency bands, modulation standards and bandwidth. Current industry solution involves parallel PAs dedicated to a single band of operation. As more and more features are added, more and more PAs will be required with increasing cost, area and complexity. As a solution to this problem, one tunable fully integrated class-F power amplifier with reconfigurable output harmonic termination is proposed, designed, fabricated and tested with a commercially available 0.13µm CMOS process technology. By using the coupling between the primary and the secondary winding of an on chip transformer with a variable secondary termination capacitance, the second and third harmonic short and open circuit frequencies are dynamically tuned from 700 MHz to 1200 MHz and achieve high efficiency and output power. To overcome CMOS process low break down voltage, a series voltage combining approach is used for the power device to boost output power, by allowing the power supply to exceed process limits. The fabricated die was packaged and mounted to a printed circuit board for evaluation. Compared to previously publish fully integrated PAs, our design exhibits superior peak power added efficiency, 48.4%, and decent saturated output power and power gain of 24.6 dBm and 16.5 dB respectively with reconfigurability from 700 MHz to 1200 MHz

Microwave class-E power amplifiers: a brief review of essential concepts in high-frequency class-E PAs and related circuits

Since Nathan Sokal's invention of the class-E power amplifier (PA), the vast majority of class-E results have been reported at kilohertz and millihertz frequencies, but the concept is increasingly applied in the ultrahigh-frequency (UHF) [1]-[13], microwave [14]-[20], and even millimeter-wave range [21]. The goal of this article is to briefly review some interesting concepts concerning high-frequency class-E PAs and related circuits. (The article on page 26 of this issue, "A History of Switching-Mode Class-E Techniques" by Andrei Grebennikov and Frederick H. Raab, provides a historical overview of class-E amplifier development.)We acknowledge support, in part, by a Lockheed Martin Endowed Chair at the University of Colorado and in part by the Spanish Ministry of Economy, Industry, and Competitiveness (MINECO) through TEC2014-58341-C4-1-R and TEC2017-83343-C4-1-R projects, cofunded with FEDER

Reconfigurable RF Front End Components for Multi-Radio Platform Applications

The multi-service requirements of the 3G and 4G communication systems, and their backward compatibility requirements, create challenges for the antenna and RF front-end designs with multi-band and wide-band techniques. These challenges include: multiple filters, which are lossy, bulky, and expensive, are needed in the system; device board size limitation and the associated isolation problems caused by the limited space and crowd circuits; and the insertion loss issues created by the single-pole-multi-through antenna switch. As will be shown, reconfigurable antennas can perform portions of the filter functions, which can help solve the multiple filters problem. Additionally, reconfigurable RF circuits can decrease the circuit size and output ports, which can help solve board size limitation, and isolation and antenna switch insertion loss issues. To validate the idea that reconfigurable antennas and reconfigurable RF circuits are a viable option for multi-service communication system, a reconfigurable patch antenna, a reconfigurable monopole antenna, and a reconfigurable power amplifier (PA) have been developed. All designs adapt state-of-the-art techniques. For the reconfigurable antenna designs, an experiment demonstrating its advantages, such as jamming signal resistance, has been performed. Reconfigurable antennas provide a better out-ofoperating- band noise performance than the multi-band antennas design, decreasing the need for filters in the system. A full investigation of reconfigurable antennas, including the single service reconfigurable antenna, the mixed signal service reconfigurable antenna, and the multi-band reconfigurable antenna, has been completed. The design challenges, which include switches investigation, switches integration, and service grouping techniques, have been discussed. In the reconfigurable PA portion, a reconfigurable PA structure has first been demonstrated, and includes a reconfigurable output matching network (MN) and a reconfigurable die design. To validate the proposed reconfigurable PA structure, a reconfigurable PA for a 3G cell phone system has been designed with a multi-chip module technique. The reconfigurable PA structure can significantly decrease the real-estate, cost, and complexity of the PA design. Further, by decreasing the number of output ports, the number of poles for the antenna switch will be decreased as well, leading to an insertion loss decrease

Reconfigurable high efficiency class-F power amplifier using CMOS-MEMS technology

The increasing demand for wireless products to be part of our daily lives brings the need for longer battery lifetime, smaller size and lower cost. To increase battery lifetime, high efficiency power amplifiers (PAs) are needed; To make them smaller, integration or reconfiguration is aimed and to reach lower costs, technologies such as CMOS are final goals. However integration of high efficiency PA in CMOS is challenging due to the technology limitations which restricts the achievable output power and efficiency of the PA. In order to bring solutions for the above-mentioned requirements, in this thesis novel reconfigurable class-F PAs, frequency-reconfiguration, CMOS integration, impedance-reconfiguration and CMOS-MEMS implementation are addressed. Starting with a single frequency operation, a novel class-F PA for mobile applications is proposed in which with a proper harmonic tuning structure the need for extra filtering sections is eliminated, achieving an excellent harmonic-suppression level. This topology uses transmission lines and is developed to cover multiple frequency bands for purpose of global coverage with aim of size reduction. Three novel frequency reconfigurable PAs are proposed using MEMS and semiconductor switches to accomplish class-F operation at two frequencies. The main novelty of this structure is that the reconfiguration is done not only at fundamental frequency but also at harmonics with reduced number of tuning elements. Moreover, by proper placement of the switches in the stubs, the maximum voltages over the switches are minimized. The proposed structure overcomes the narrow band performance of class-F, giving an efficiency more than 60% over a 225 MHz and 175 MHz bandwidth at 900 MHz and 1800 MHz respectively. Measurement results showed high performance at both frequency bands giving 69.5% and 57.9% PAE at 900 MHz and 1800 MHz respectively. A novel CMOS class-F PA is proposed that controls up to the 3rd harmonic and can adapt to load variations due to the effect of the human body on mobile phones. It enables the integration of the PA with other devices in a single chip leading to better matching, higher performance, lower cost and smaller size. In addition, it achieves load impedance reconfigurability by using impedance tuner in its output network and by proper tuning of the network, effects of load variation on the performance are compensated. Two designs at 2.4 GHz have been done using either MOS varactors or MEMS variable capacitors as tuning devices. The design using MOS varactors show a maximum measured values of 26% PAE and 19.2 dBm output power for 50 load. For loads other than 50 ohm an improvement of 15% for PAE and 4.4 dB for output power is obtained in comparison to non-tuned one. The second design is done using MEMS variable capacitors integrated in CMOS technology through a mask-less post-processing technique. Simulations results for 50 ohm load show a peak PAE of 32.8% while delivering 18.2 dBm output power.La creixent demanda de productes sense fils en la nostra vida diària requereix dispositius de menor grandària, menor cost i amb una gran autonomia. Per reduir la mida i augmentar l'autonomia és necessari utilitzar sistemes integrats multiestàndard o reconfigurables, amb amplificadors de RF d'alta eficiència, mentre que per reduir el cost, és preferible utilitzar tecnologies econòmiques com CMOS. No obstant això, la integració en CMOS d'amplificadors de radiofreqüència, i en especial, d'alta eficiència, és un repte a causa de les limitacions de la tecnologia que restringeixen la potència de sortida realitzable i l'eficiència de l'amplificador. En aquesta tesi es tracten els diferents reptes anteriorment esmentats, proposant una nova topologia d'amplificador classe-F amb reconfiguració de freqüència, i proposant la integració d'un amplificador classe-F que s¿adapta a impedància de càrrega variable, implementat en CMOS i CMOS-MEMS. Inicialment en la tesi es proposa una topologia d'amplificador classe-F en què, gràcies a una estructura adequada a la xarxa d'adaptació, s¿elimina la necessitat de filtrat extra, aconseguint un nivell de rebuig d'harmònics excel·lent. La topologia proposada utilitza línies de transmissió i s'ha desenvolupat per dues bandes diferents, amb el disseny orientat a implementar un sistema reconfigurable. S'han aconseguit PAE de l'ordre del 80 % amb potències properes a 10 W. Un cop descrita i analitzada la topologia, s'han proposat tres amplificadors reconfigurables per doble banda freqüencial. Per a la reconfiguració s'han utilitzat MEMS i commutadors basats en semiconductors. L'estructura proposada permet la reconfiguració no només en la freqüència fonamental sinó també en els harmònics, però mantenint un nombre reduït d'elements d'ajust. A més, gràcies a l'adequada col·locació dels commutadors en les línies de transmissió, s'ha minimitzat la tensió màxima en els mateixos. Així mateix, l'estructura proposada evita la característica de banda estreta a classe-F, proporcionant una eficiència superior al 60% en unes amplades de banda de 225 MHz i de 175 MHz, per a les banda de 900 MHz i 1800 MHz respectivament. En aquestes bandes, la PAE màxima mesurada és del 69,5% i del 57,9% respectivament. Finalment, s'ha proposat un amplificador integrat en CMOS, classe-F amb control fins al tercer harmònic. L'amplificador proposat incorpora un sintonitzador a la sortida, podent així adaptar-se a variacions d'impedància de càrrega, típiques en dispositius sense fil (WLAN), degudes a l'efecte del cos humà sobre l'antena. La implementació en CMOS permet la integració de l'amplificador de potència amb altres dispositius en un únic xip, donant lloc a una millor adaptació, millor rendiment, menor cost i menor grandària del sistema. A més, gràcies a l'adaptació a les variacions de la impedància de càrrega, permet mantenir el rendiment en diferents rangs d'operació. S'han realitzat dos dissenys de l'amplificador a 2,4 GHz, un basat en varactors MOS i un altre en condensadors variables MEMS. El disseny que utilitza varactors MOS mostra una PAE màxima del 26% i una potència de 19,2 dBm per a càrrega adaptada 50 ohm. Per altres càrregues, gràcies a l'adaptació d'impedància, s'obté una millora de PAE del 15% i de 4,4 dB en potència de sortida. El disseny utilitzant condensadors MEMS s'integra en CMOS gràcies a post-processat sense màscares addicionals. Els resultats de simulació per a 50 ohm mostren una PAE del 32,8% per 18,2 dBm de potència de sortid