Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion

Extended-Range Second-Order Incremental Sigma-Delta ADC

A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion).A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion)

Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH

Ultra-low power incremental delta-sigma analog-to-digital converter for self-powered sensor applications

Tässä työssä esitetään ultramatalatehoinen inkrementaalinen delta-sigma-analogia-digitaalimuunnin. Muunnin on suunniteltu 0,18 μm:n CMOS-teknologialla, ja se toimii 1,2 V :n käyttöjännitteellä ja 5 kHz:n kellotaajuudella. Differentiaalinen tulosignaali on käytännössä dc:llä, ja se vaihtelee 600 mV :n yhteismuotoisen jännitteen ympärillä -850 mV :sta 850 mV :iin. Delta-sigmamodulaattorissa käytetään kaksiasteista takaisinkytkettyä integraattorikaskadirakennetta, joka on toteutettu kytketty-kondensaattori-integraattoreilla ja yksibittisellä kvantisoijalla. Muuntimen kvantisointikohinavaatimuksien täyttyminen varmistettiin valitsemalla sopivat kertoimet ja ylinäytteistyssuhde käyttäen MATLAB-simulaatioita yhdessä modulaattorin ideaalisen mallin kanssa. Vahvistinten vähimmäisvaatimukset määritettiin makromallitason simuloinneilla ja kytkinten epäideaalisuudet analysoitiin transistoritason simuloinneilla. Varausinjektion huomattiin aiheuttavan piirissä merkittävää harmonista säröä, joten alalevyn näytteistystä (bottom plate sampling) käytettiin signaaliriippuvan varausinjektion välttämiseksi. Lisäksi ensimmäisen integraattorin vahvistimen tulonsiirrosjännitteen ja matalataajuisen kohinan vähentämiseksi käytettiin hakkuristabilointia (chopper stabilization). Muuntimen suorituskykyä analysoitiin eri prosessikulmissa lämpötiloissa −40 ◦ C, 27 ◦ C ja 85 ◦ C, ja epäsovitusherkkyys määritettiin Monte Carlo -analyysin avulla. Simulaatiotulokset sekä piirikuvion perusteella lasketut parasiittiset resistanssit ja kapasitanssit huomioonottaen, että ilman, osoittavat piirin olevan stabiili ja täyttävän tarkkuusvaatimukset kaikissa simuloiduissa kulmissa. Monta Carlo -analyysin perusteella signaali-kohinasuhde on vähintään 80,05 dB:ä ja harmonisen särön kokonaismäärä on enintään -80.89 dB:ä. Tehonkulutus ei ylitä 1,2 μA:a missään simulaatiossa.In this thesis an ultra-low power incremental delta-sigma analog-to-digital converter is presented. The converter is designed in 0.18 μm CMOS technology with a single 1.2 V supply voltage, and it operates with a 5 kHz clock signal. The differential input signal to the converter is virtually dc, and it varies from −850 mV to 850 mV around a common-mode voltage of 600 mV . The delta-sigma modulator has a second order cascade-of-integrators feedback structure, which is realized with switched-capacitor integrators and a one-bit quantizer. The converter’s quantization noise requirement is met by appropriate choice of coefficients and oversampling ratio, based on MATLAB simulations on an ideal model of the modulator. The minimum requirements of the amplifiers were determined from simulations with macromodels, and the switch non-idealities were analyzed in transistor-level simulations. It was noticed that switch charge injection causes significant harmonic distortion in the circuit, hence bottom plate sampling was implemented to eliminate the signal-dependent charge injection. Furthermore, the offset and low-frequency noise in the first integrator were attenuated by means of chopper stabilization. The converter’s performance is analyzed in different process corners, at −40◦ C, 27◦ C, and 85◦ C, and its process mismatch sensitivity is determined via Monte Carlo analysis. The results obtained from both pre- and post-layout simulations indicate complete stability, and acceptable accuracy in all design corners. The minimum signal-to-noise and distortion ratio obtained from corner analysis, is 80.05 dB, which is enhanced up to 7 dB in the best corner, and maximum harmonic distortion is below −80.89 dB. Moreover, the power consumption of the converter did not exceed 1.2 μW in any of the simulations

Doctor of Philosophy

dissertationAdvancements in process technology and circuit techniques have enabled the creation of small chemical microsystems for use in a wide variety of biomedical and sensing applications. For applications requiring a small microsystem, many components can be integrated onto a single chip. This dissertation presents many low-power circuits, digital and analog, integrated onto a single chip called the Utah Microcontroller. To guide the design decisions for each of these components, two specific microsystems have been selected as target applications: a Smart Intravaginal Ring (S-IVR) and an NO releasing catheter. Both of these applications share the challenging requirements of integrating a large variety of low-power mixed-signal circuitry onto a single chip. These applications represent the requirements of a broad variety of small low-power sensing systems. In the course of the development of the Utah Microcontroller, several unique and significant contributions were made. A central component of the Utah Microcontroller is the WIMS Microprocessor, which incorporates a low-power feature called a scratchpad memory. For the first time, an analysis of scaling trends projected that scratchpad memories will continue to save power for the foreseeable future. This conclusion was bolstered by measured data from a fabricated microcontroller. In a 32 nm version of the WIMS Microprocessor, the scratchpad memory is projected to save ~10-30% of memory access energy depending upon the characteristics of the embedded program. Close examination of application requirements informed the design of an analog-to-digital converter, and a unique single-opamp buffered charge scaling DAC was developed to minimize power consumption. The opamp was designed to simultaneously meet the varied demands of many chip components to maximize circuit reuse. Each of these components are functional, have been integrated, fabricated, and tested. This dissertation successfully demonstrates that the needs of emerging small low-power microsystems can be met in advanced process nodes with the incorporation of low-power circuit techniques and design choices driven by application requirements