7 research outputs found
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Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps
This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired signal on a capacitor during an "estimate" phase, and subtracting the signal from the active circuitry (typically an opamp) during a "level shift" phase. This is done within the confines of a feedback loop. The effective loop-gain is the product of the loop-gains during the estimate and level shift phases. This enables, for example, a two-stage opamp to have the accuracy of a four-stage opamp. It also enables full utilization of the power supply since the gain block's output voltage can exceed the power supply. The thesis shows that the full utilization of the power supply and the increased DC effective loop gain leads to a significant power savings compared to existing techniques.
The methods are presented in the context of pipelined analog-to-digital converters, although the methods can be used with other circuits that use opamps or are sensitive to component mismatch. An overview of the detrimental effects of reduced signal swing and low DC gain is given with an emphasis on the cost in power to correct these deficiencies when limited to existing circuit techniques. CLS is then shown to correct these deficiencies without increasing power. A detailed explanation of CLS operation is given, as are measured results from a 12-bit pipelined analog-to-digital converter that was fabricated using a 0.18Ī¼ CMOS process. The results include greater than 10-bit performance with true rail-to-rail operation.
An overview of calibration is also given and the limitations are discussed. An argument is made that using CLS in addition to calibration will reduce power by increasing signal-to-noise ratio and reducing and linearizing the errors due to finite opamp gain. In addition, a method to reduce the effects of mismatch by measuring the relative size of elements is presented.
Finally, several avenues for future research into CLS are given
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Ring Amplifier Optimized for High Resolution Analog-to-Digital Converter Applications
In recent years, SAR ADCs have been shown to acheive faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such as the two-step SAR. The two-step SAR ADC, also known as pipelined SAR ADC, combine the concepts of SAR and Pipeline ADC architecture where a residue amplifier provides a critical amplification step. An amplifier architecture well suited for residue amplification known as Ring Amplifier (RAMP) has enabled power efficient two-step SAR ADCs. However, RAMP based ADCs with greater than 14 bits of resolution has not been attempted in previous literature. In this work, the design and measurement of a high-resolution two-step SAR ADC utilizing an enhanced RAMP is demonstrated. Additional circuit techniques are introduced that contribute to the energy-efficiency of the ADC. The ADC implemented in 0.18m technology achieves a DR of 95dB and a Schreier FOM better than 180dB at both 2MS/s and 15MS/s
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A multi-bit hybrid DSM over full-scale range without feedback DEM
Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) speciļ¬cations. Among various ADCs, a āĪ£ ADC is best known as a power-eļ¬cient ADC when more than 12b is required. However, a conventional discrete-time (DT) āĪ£ Modulator (āĪ£M) is inadequate for low-power wideband applications due to the opamp settling requirement. Alternatively, a continuous-time (CT) āĪ£M can be used to decrease power consumption but has its own disadvantages such as clock jitter sensitivity, RC time constant variation, and excess loop delay.
The wideband modulators are often implemented as single-loop high-order modulators in a deep submicron process. The high-order modulator typically has a quantizer overloading problem as the input signal approaches to a full-scale range.
A pole-optimization method can be used to extend the linear input range but it
inevitably decreases signal to quantization noise ratio. This causes power penalty
since it limits the maximum input power available.
Another challenge is linearizing a nonlinear multi-bit Digital-to-Analog Converter (DAC). On one hand, the DAC can be linearized by element sizing, sorting,
and calibration but these increase silicon area and power consumption. On the
other hand, a Dynamic Element Matching algorithm (DEM) linearizes the DAC
by averaging and shaping the mismatches with minimal design overhead. However, the DEM causes additional delay inside the feedback path. This can make the modulator unstable.
In this thesis, a multi-bit 3rd-order hybrid āĪ£M with over full-scale range
and no DEM in the critical feedback path is presented. Removing the DEM in the
critical path enables the modulator to minimize latency in the feedback path. A
digital feedforward structure allows processing the input signal over the full-scale reference voltage. Combined beneļ¬ts of the CT/DT implementation help to reduce power consumption and to mitigate the loop delay. Measurement results from a
prototype demonstrate the eļ¬ectiveness of the proposed ideas
Time interleaved counter analog to digital converters
The work explores extending time interleaving in A/D converters, by
applying a high-level of parallelism to one of the slowest and simplest types of
data-converters, the counter ADC. The motivation for the work is to realise
high-performance re-configurable A/D converters for use in multi-standard and
multi-PHY communication receivers with signal bandwidths in the 10s to 100s of
MHz. The counter ADC requires only a comparator, a ramp signal, and a
digital counter, where the comparator compares the sampled input against all
possible quantisation levels sequentially. This work explores arranging counter
ADCs in large time-interleaved arrays, building a Time Interleaved Counter
(TIC) ADC. The key to realising a TIC ADC is distributed sampling and a
global multi-phase ramp generator realised with a novel figure-of-8 rotating
resistor ring. Furthermore Counter ADCs allow for re-configurability between
effective sampling rate and resolution due to their sequential comparison of
reference levels in conversion. A prototype TIC ADC of 128-channels was
fabricated and measured in 0.13Ī¼m CMOS technology, where the same block can
be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter.
The ADC achieves a sub 400fJ/step FOM in all modes of
configuration
Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers
In the field of radio receivers, down-conversion methods usually rely on one (or more)
explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not
only contribute to the overall power consumption but also have an impact on area and can
compromise the receiverās performance in terms of noise and linearity. On the other hand,
most ADCs require some sort of reference signal in order to properly digitize an analog
input signal. The implementation of this reference signal usually relies on bandgap
circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this
conventional approach, the work developed in this thesis aims to explore the viability
behind the usage of a variable reference signal. Moreover, it demonstrates that not only
can an input signal be properly digitized, but also shifted up and down in frequency,
effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver
chains can perform double-duty as both a quantizer and a mixing stage. The lesser known
charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs,
is used for a practical implementation, due to its feature of āpre-chargingā the reference
signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in
a 0.13 Ī¼m CMOS technology validate the proposed technique
Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs
During the past decade, SAR ADCs have enjoyed increasing prominence due to their
inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however
most of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu-
tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC element
mismatch constraints are critical but not insurmountable at 10 bits of resolution or less in
sub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs
(11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraint
still dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors.
The focus of this work is to extend the scaling benefits of the SAR architecture to medium
and higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138630/1/ncolins_1.pd
Wireless Sensor Networks
The aim of this book is to present few important issues of WSNs, from the application, design and technology points of view. The book highlights power efficient design issues related to wireless sensor networks, the existing WSN applications, and discusses the research efforts being undertaken in this field which put the reader in good pace to be able to understand more advanced research and make a contribution in this field for themselves. It is believed that this book serves as a comprehensive reference for graduate and undergraduate senior students who seek to learn latest development in wireless sensor networks