Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter. Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18µm CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10’s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter

Simulation and Design of an UWB Imaging System for Breast Cancer Detection

Breast cancer is the most frequently diagnosed cancer among women. In recent years, the mortality rate due to this disease is greatly decreased thanks to both enormous progress in cancer research, and screening campaigns which have allowed the increase in the number of early diagnoses of the disease. In fact, if the tumor is identied in its early stage, e.g. when it has a diameter of less than one centimeter, the possibility of a cure can reach 93%. However, statistics show that more young aged women are suered breast cancer. The goal of screening exams for early breast cancer detection is to nd cancers before they start to cause symptoms. Regular mass screening of all women at risk is a good option to achieve that. Instead of meeting very high diagnostic standards, it is expected to yield an early warning, not a denitive diagnosis. In the last decades, X-ray mammography is the most ecient screening technique. However, it uses ionizing radiation and, therefore, should not be used for frequent check-ups. Besides, it requires signicant breast compression, which is often painful. In this scenario many alternative technologies were developed to overcome the limitations of mammography. Among these possibilities, Magnetic Resonance Imaging (MRI) is too expensive and time-consuming, Ultrasound is considered to be too operatordependent and low specicity, which are not suitable for mass screening. Microwave imaging techniques, especially Ultra WideBand (UWB) radar imaging, is the most interesting one. The reason of this interest relies on the fact that microwaves are non-ionizing thus permitting frequent examinations. Moreover, it is potentially lowcost and more ecient for young women. Since it has been demonstrated in the literatures that the dielectric constants between cancerous and healthy tissues are quite dierent, the technique consists in illuminating these biological tissues with microwave radiations by one or more antennas and analyzing the re ected signals. An UWB imaging system consists of transmitters, receivers and antennas for the RF part, the transmission channel and of a digital backend imaging unit for processing the received signals. When an UWB pulse strikes the breast, the pulse is re ected due to the dielectric discontinuity in tissues, the bigger the dierence, the bigger the backscatter. The re ected signals are acquired and processed to create the energy maps. This thesis aims to develop an UWB system at high resolution for the detection of carcinoma breast already in its initial phase. To favor the adoption of this method in screening campaigns, it is necessary to replace the expensive and bulky RF instrumentation used so far with ad-hoc designed circuits and systems. In order to realize that, at the very beginning, the overall system environment must be built and veried, which mainly consists of the transmission channel{the breast model and the imaging unit. The used transmission channel data come from MRI of the prone patient. In order to correctly use this numerical model, a simulator was built, which was implemented in Matlab, according to the Finite-Dierence-Time- Domain (FDTD) method. FDTD algorithm solves the electric and magnetic eld both in time and in space, thus, simulates the propagation of electromagnetic waves in the breast model. To better understand the eect of the system non-idealities, two 2D breast models are investigated, one is homogeneous, the other is heterogeneous. Moreover, the modeling takes into account all critical aspects, including stability and medium dispersion. Given the types of tissues under examination, the frequency dependence of tissue dielectric properties is incorporated into wideband FDTD simulations using Debye dispersion parameters. A performed further study is in the implementation of the boundary conditions. The Convolution Perfectly Matched Layer (CPML) is used to implement the absorbing boundaries. The objective of the imaging unit is to obtain an energy map representing the amount of energy re ected from each point of the breast, by recombining the sampled backscattered signals. For this purpose, the study has been carried out on various beamforming in the literature. The basic idea is called as "delay and sum", which is to align the received signals in such a way as to focus a given point in space and then add up all the contributions, so as to obtain a constructive interference at that point if this is a diseased tissue. In this work, Microwave Imaging via Space Time (MIST) Beamforming algorithm is applied, which is based on the above principle and add more elaborations of the signals in order to make the algorithm less sensitive to propagation phenomena in the medium and to the non-idealities of the system. It is divided into two distinct steps: the rst step, called SKin Artifact Removal (SKAR), takes care of removing the contributions from the signal caused by the direct path between the transmitter and receiver, the re ection of skin, as they are orders of magnitude higher compared to the re ections caused by cancers; the second step, which is BEAmForming (BEAF), performs the algorithm of reconstruction by forming a weighted combination of time delayed version of the calibrated re ected signals. As discussed above, more attention must be paid on the implementation of the ad-hoc integration circuits. In this scenario, due to the strict requirements on the RF receiver component, two dierent approaches of the implementation of the RF front-end, Direct Conversion (DC) receiver and Coherent Equivalent Time Sampling (CETS) receiver are compared. They are modeled behaviorally and the eects of various impairments, such as thermal, jitter, and phase noise, as well as phase inaccuracies, non-linearity, ADC quantization noise and distortion, on energy maps and on quantitative metrics such as SCR and SMR are evaluated. Dierential Gaussian pulse is chosen as the exciting source. Results show that DC receiver performs higher sensitivity to phase inaccuracies, which makes it less robust than the CETS receiver. Another advantage of the CETS receiver is that it can work in time domain with UWB pulses, other than in frequency domain with stepped frequency continuous waves like the DC one, which reduces the acquisition time without impacting the performance. Based on the results of the behavioral simulations, low noise amplier (LNA) and Track and Hold Amplier (THA) can be regarded as the most critical parts for the proposed CETS receiver, as well as the UWB antenna. This work therefore focuses on their hardware implementations. The LNA, which shows critical performance limitation at bandwidth and noise gure of receiver, has been developed based on common-gate conguration. And the THA based on Switched Source Follower (SSF) scheme has been presented and improved to obtain high input bandwidth, high sampling rate, high linearity and low power consumption. LNA and THA are implemented in CMOS 130nm technology and the circuit performance evaluation has been taken place separately and together. The small size UWB wide-slot antenna is designed and simulated in HFSS. Finally, in order to evaluate the eect of the implemented transistor level components on system performance, a multi-resolution top-down system methodology is applied. Therfore, the entire ow is analyzed for dierent levels of the RF frontend. Initially the system components are described behaviorally as ideal elements. The main activity consists in the analysis and development of the entire frontend system, observing and complementing each other blocks in a single ow simulation, clear and well-dened in its various interfaces. To achieve that the receiver is modeled and analyzed using VHDL-AMS language block by block, moreover, the impact of quantization, noise, jitter, and non-linearity is also evaluated. At last, the behavioral description of antenna, LNA and THA is replaced with a circuit-level one without changing the rest of the system, which permits a system-level assessment of low-level issues

Conversion analogique-numérique Sigma-Delta large bande appliquée à la mesure des non-linéarités des amplificateurs de puissance

Power amplifiers, which are essential elements of any communication system, will play a crucial role in the development of future communication systems. Today improving power amplifiers requires technological advances at the circuit device level, but one also must consider a more global approach. In particular, advances in digital processing can now correct in the early stage of the communication chain some distortions that are generated downstream in the chain. Digital pre-distortion is a correction technique for power amplifiers that has a growing interest because of its completely digital implementation and of its gains in linearity and energy consumption. This technique requires a feedback path where the analog-to-digital converter is a critical element. This component must satisfy the constraints of high resolution , wide bandwidth, and high linearity. In this thesis, we propose a new architecture of analog-to-digital converter based on bandpass Delta-Sigma modulators. This architecture takes advantage of operating bandpass modulators that are designed to work in parallel, each focusing on different frequencies, but also of a particular cascading arrangement to eliminate the useful signal, which has a high power, in order to reduce dynamics constraints. High-level design and simulations were carried out for discrete time and continuous time systems and also required the development of appropriate simulation tools.Les amplificateurs de puissance, éléments constitutifs essentiels de tout système de télécommunication, vont jouer un rôle capital dans le développement des futurs systèmes de communication. Aujourd'hui l'amélioration des amplificateurs de puissance nécessite un progrès technologique au niveau du composant lui même mais doit aussi tenir compte d'une approche plus globale. En particulier, le progrès dans les traitements numériques permet aujourd'hui de corriger en amont certaines distorsions qui seront générées en aval de la chaîne de communication. La pré-distorsion numérique est une technique de correction des amplificateurs de puissance qui connaît un intérêt grandissant de par son intégration complètement numérique et par les gains en linéarité et en consommation. Cette technique nécessite une voie de retour dont un élément critique est le convertisseur analogique-numérique. Ce composant doit répondre à des contraintes de résolution, de bande passante et de linéarité élevées. Dans cette thèse, nous proposons une nouvelle architecture de convertisseur analogique-numérique à base de modulateurs Sigma-Delta passe-bande. Cette architecture tire partie du fonctionnement passe bande des modulateurs que nous faisons travailler en parallèle, chacun centré sur différentes fréquences, mais aussi d'un agencement en cascade particulier pour éliminer le signal utile, qui est de forte puissance, dans le but de diminuer les contraintes de dynamique.La conception haut niveau et les simulations ont été menées pour des systèmes à temps discret et aussi à temps continu et a nécessité le développement d'outils adaptés de simulation se basant sur la boîte à outils Delta Sigma Toolbox de Richard Schreie