Chip Implementation with a Combined Wireless Temperature Sensor and Reference Devices Based on the DZTC Principle

This paper presents a novel CMOS wireless temperature sensor design in order to improve the sensitivity and linearity of our previous work on such devices. Based on the principle of CMOS double zero temperature coefficient (DZTC) points, a combined device is first created at the chip level with two voltage references, one current reference, and one temperature sensor. It was successfully fabricated using the 0.35 μm CMOS process. According to the chip results in a wide temperature range from −20 °C to 120 °C, two voltage references can provide temperature-stable outputs of 823 mV and 1,265 mV with maximum deviations of 0.2 mV and 8.9 mV, respectively. The result for the current reference gives a measurement of 23.5 μA, with a maximum deviation of 1.2 μA. The measurements also show that the wireless temperature sensor has good sensitivity of 9.55 mV/°C and high linearity of 97%. The proposed temperature sensor has 4.15-times better sensitivity than the previous design. Moreover, to facilitate temperature data collection, standard wireless data transmission is chosen; therefore, an 8-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 433 MHz wireless transmitter are also integrated in this chip. Sensing data from different places can be collected remotely avoiding the need for complex wire lines

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Voyager electronic parts radiation program, volume 1

The Voyager spacecraft is subject to radiation from external natural space, from radioisotope thermoelectric generators and heater units, and from the internal environment where penetrating electrons generate surface ionization effects in semiconductor devices. Methods for radiation hardening and tests for radiation sensitivity are described. Results of characterization testing and sample screening of over 200 semiconductor devices in a radiation environment are summarized

Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications

The instrumentation of radiation detectors for high energy physics calls for the development of very low-noise application-specific integrated-circuits and demanding system-level design strategies, with a particular focus on the minimisation of inter-ference noise from power anagement circuitry. On the other hand, the aggressive pixelisation of sensors and associated front-end electronics, and the high radiation exposure at the innermost tracking and vertex detectors, requires radiation-aware design and radiation-tolerant deep sub-micron CMOS technologies. This thesis explores circuit design techniques towards radiation tolerant power management integrated circuits, targeting applications on particle detectors and monitoring of accelerator-based experiments, aerospace and nuclear applications. It addresses advantages and caveats of commonly used radiation-hard layout techniques, which often employ Enclosed Layout or H-shaped transistors, in respect to the use of linear transistors. Radiation tolerant designs for bandgap circuits are discussed, and two different topologies were explored. A low quiescent current bandgap for sub-1 V CMOS circuits is proposed, where the use of diode-connected MOSFETs in weak-inversion is explored in order to increase its radiation tolerance. An any-load stable LDO architecture is proposed, and three versions of the design using different layout techniques were implemented and characterised. In addition, a switched DC-DC Buck converter is also studied. For reasons concerning testability and silicon area, the controller of the Buck converter is on-chip, while the inductance and the power transistors are left on-board. A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. The chip features Linear, ELT and H-shape LDO designs, bandgap circuits and a Buck DC-DC converter. We discuss the design, layout and test results of the prototype. The specifications in terms of voltage range and output current capability are based on the requirements set for the integrated on-detector electronics of the new CGEM-IT tracker for the BESIII detector. The thesis discusses the fundamental aspects of the proposed on-detector electronics and provides an in-depth depiction of the front-end design for the readout ASIC

Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

JPL preferred parts list: Reliable electronic components

The JPL Preferred Parts List was prepared to provide a basis for selection of electronic parts for JPL spacecraft programs. Supporting tests for the listed parts were designed to comply with specific spacecraft environmental requirements. The list tabulates the electronic, magnetic, and electromechanical parts applicable to all JPL electronic equipment wherein reliability is a major concern. The parts listed are revelant to equipment supplied by subcontractors as well as fabricated at the laboratory

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Low-Power Integrated Circuits For Biomedical Applications

With thousands new cases of spinal cord injury reported everyday, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs, such a state severely deteriorates the patients' quality of life and may even lead to additional medical conditions. Therefore, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient's brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts, having high spatial resolution and signal to noise ratio, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted. To implement a fully implantable system, low-power and miniaturized electronics are needed to reduced heat generation, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system's components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system, namely, ultra low-power brain signal acquisition front-ends, a low-power and inductorless MedRadio transceiver, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillator generates the reference signal for other system's components such as analog to digital converter. Novel techniques to improve important performance parameters (power consumption, low noise operation and interference resilience) have been introduced. Electrical, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design

Technical Design Report for PANDA Electromagnetic Calorimeter (EMC)

This document presents the technical layout and the envisaged performance of the Electromagnetic Calorimeter (EMC) for the PANDA target spectrometer. The EMC has been designed to meet the physics goals of the PANDA experiment. The performance figures are based on extensive prototype tests and radiation hardness studies. The document shows that the EMC is ready for construction up to the front-end electronics interface