Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

Communication and energy delivery architectures for personal medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 219-232).Advances in sensor technologies and integrated electronics are revolutionizing how humans access and receive healthcare. However, many envisioned wearable or implantable systems are not deployable in practice due to high energy consumption and anatomically-limited size constraints, necessitating large form-factors for external devices, or eventual surgical re-implantation procedures for in-vivo applications. Since communication and energy-management sub-systems often dominate the power budgets of personal biomedical devices, this thesis explores alternative usecases, system architectures, and circuit solutions to reduce their energy burden. For wearable applications, a system-on-chip is designed that both communicates and delivers power over an eTextiles network. The transmitter and receiver front-ends are at least an order of magnitude more efficient than conventional body-area networks. For implantable applications, two separate systems are proposed that avoid reimplantation requirements. The first system extracts energy from the endocochlear potential, an electrochemical gradient found naturally within the inner-ear of mammals, in order to power a wireless sensor. Since extractable energy levels are limited, novel sensing, communication, and energy management solutions are proposed that leverage duty-cycling to achieve enabling power consumptions that are at least an order of magnitude lower than previous work. Clinical measurements show the first system demonstrated to sustain itself with a mammalian-generated electrochemical potential operating as the only source of energy into the system. The second system leverages the essentially unlimited number of re-charge cycles offered by ultracapacitors. To ease patient usability, a rapid wireless capacitor charging architecture is proposed that employs a multi-tapped secondary inductive coil to provide charging times that are significantly faster than conventional approaches.by Patrick Philip Mercier.Ph.D

Development of an L-, C-, and X-band radar for backscattering studies over vegetation

With the recent surge of interest in global change, the impact of different ecosystems on the Earth's carbon budget has become the focus of many scientific studies. Studies have been launched by NASA and other agencies to address this issue. One such study is the Boreal Ecosystem-Atmosphere Study (BOREAS). BOREAS focuses on the boreal ecosystem in Northern Canada. As a part of the BOREAS study, we have developed a helicopter-borne three-band radar system for measuring the scattering coefficient of various stands within the boreal forest. During the summer of 1994 the radar was used at the southern study area (SSA) in Saskatchewan over the young jack pine (YJP), old jack pine (OJP), old black spruce (OBS) and old aspen (OA) sites. The data collected will be used to study the interaction of microwaves with forest canopy. By making use of three different frequency bands the contribution to the backscatter from each of the layers within the canopy can be determined. Using the knowledge gained from these studies, we will develop algorithms to enable more accurate interpretation of SAR images of the boreal region. This report describes in detail the development of the L-, C- and X-band radar system. The first section provides background information and explains the objectives of the boreal forest experiment. The second section describes the design and implementation of the radar system. All of the subsystems of the radar are explained in this section. Next, problems that were encountered during system testing and the summer experiments are discussed. System performance and results are then presented followed by a section on conclusions and further work

ATS-6 engineering performance report. Volume 3: Telecommunications and power

Functional design requirements and in-orbit operations, performance, and anomalies are discussed for (1) the communications subsystem, (2) the electrical power system, and (3) the telemetry and command subsystem. The latter includes a review of ground support. Tracking and data relay experiments and the Apollo-Soyuz test program are reviewed

Energy efficient control for power management circuits operating from nano-watts to watts

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 163-172).Energy efficiency and form factor are the key driving forces in today's power electronics. All power delivery circuits, irrespective of the magnitude of power, basically consists of power trains, gate drivers and control circuits. Although the control circuits are primarily required for regulation, these circuits can play a crucial role in achieving high efficiency and/or minimizing overall system form-factor. In this thesis, power converter circuits, spanning a wide operating range- from nano-watts to watts, are presented while highlighting techniques for using digital control circuits not just for regulation but also to achieve high system efficiency and smaller system form-factor. The first part of the thesis presents a power management unit of an autonomous wireless sensor that sustains itself by harvesting energy from the endo-cochlear potential (EP), the 70-100mV electrochemical potential inside the mammalian inner ear. Due to the anatomical constraints, the total extractable power from the EP is limited to 1.1-6.3nW. A low switching frequency boost converter is employed to increase the input voltage to a higher voltage usable by CMOS circuits in the sensor. Ultra-low power digital control circuits with timers help keep the quiescent power of the power management unit down to 544pW. Further, a charge-pump is used to implement leakage reduction techniques in the sensor. This work demonstrates how digital low power control circuit design can help improve converter efficiency and ensure system sustainability. All circuits have been implemented on a 0.18[mu]m CMOS process. The second part of the thesis discusses an energy harvesting architecture that combines energy from multiple energy harvesting sources- photovoltaic, thermoelectric and piezoelectric sources. Digital control circuits that configure the power trains to new efficient system architectures with maximum power point tracking are presented, while using a single inductor to combine energy from the aforementioned energy sources all at the same time. A dual-path architecture for energy harvesting systems is proposed. This provides a peak efficiency improvement of 11-13% over the traditional two stage approach. The system can handle input voltages from 20mV to 5V and is also capable of extracting maximum power from individual harvesters all at the same time utilizing a single inductor. A proposed completely digital timebased power monitor is used for achieving maximum power point tracking for the photovoltaic harvester. This has a peak tracking efficiency of 96%. The peak efficiencies achieved with inductor sharing are 83%, 58% and 79% for photovoltaic boost, thermoelectric boost and piezoelectric buck-boost converters respectively. The switch matrix and the control circuits are implemented on a 0.35pm CMOS process. This part of the thesis highlights how digital control circuits can help reconfigure power converter architectures for improving efficiency and reducing form-factors. The last part of the thesis deals with a power management system for an offline 22W LED driver. In order to reduce the system form factor, Gallium Nitride (GaN) transistors capable of high frequency switching have been utilized with a Quasi-Resonant Inverted Buck architecture. A burst mode digital controller has been used to perform dimming control and power factor correction (PFC) for the LED driver. The custom controller and driver IC was implemented in a 0.35[mu]m CMOS process. The LED driver achieves a peak efficiency of 90.6% and a 0.96 power factor. Due to the high power level of the driver, the digital controller is primarily used for regulation purposes in this system, although the digital nature of the controller helps remove the passives that would be normally present in analog controllers. In this thesis, apart from regulation, control circuit enabled techniques have been used to improve efficiency and reduce system form factor. Low power design and control for reconfigurable power train architectures help improve the overall power converter efficiency. Digital control circuits have been used to reduce the form factor by enabling inductor sharing in a system with multiple power converters or by removing the compensator passives.by Saurav Bandyopadhyay.Ph.D

Systems design study of the Pioneer Venus spacecraft. Appendices to volume 1, sections 8-11 (part 3 of 3)

Power subsystem cost/weight tradeoffs are discussed for the Venus probe spacecraft. The cost estimations of power subsystem units were based upon DSCS-2, DSP, and Pioneer 10 and 11 hardware design and development and manufacturing experience. Parts count and degree of modification of existing hardware were factored into the estimate of manufacturing and design and development costs. Cost data includes sufficient quantities of units to equip probe bus and orbiter versions. It was based on the orbiter complement of equipment, but the savings in fewer slices for the probe bus balance the cost of the different probe bus battery. The preferred systems for the Thor/Delta and for the Atlas/Centaur are discussed. The weights of the candidate designs were based upon slice or tray weights for functionally equivalent circuitry measured on existing hardware such as Pioneers 10 and 11, Intelsat 3, DSCS-2, or DSP programs. Battery weights were based on measured cell weight data adjusted for case weight or off-the-shelf battery weights. The solar array weight estimate was based upon recent hardware experience on DSCS-2 and DSP arrays

An implantable micro-system for neural prosthesis control and sensory feedback restoration in amputees

In this work, the prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of two Integrated Circuits (ICs): a standard CMOS device for neural recording and a High Voltage (HV) CMOS device for neural stimulation. The integrated circuits have been realized in two different 0.35μm CMOS processes available fromAustriaMicroSystem(AMS). The recoding IC incorporates 8 channels each including the analog front-end and the A/D conversion based on a sigma delta architecture. It has a total area of 16.8mm2 and exhibits an overall power consumption of 27.2mW. The neural stimulation IC is able to provide biphasic current pulses to stimulate 8 electrodes independently. A voltage booster generates a 17V voltage supply in order to guarantee the programmed stimulation current even in case of high impedances at the electrode-tissue interface in the order of tens of k­. The stimulation patterns, generated by a 5-bit current DAC, are programmable in terms of amplitude, frequency and pulse width. Due to the huge capacitors of the implemented voltage boosters, the stimulation IC has a wider area of 18.6mm2. In addition, a maximum power consumption of 29mW was measured. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μVrms , and to selectively elicit the tibial and plantarmuscles using different active sites of the electrode. In order to get a completely implantable interface, a biocompatible and biostable package was designed. It hosts the developed ICs with the minimal electronics required for their proper operation. The package consists of an alumina tube closed at both extremities by two ceramic caps hermetically sealed on it. Moreover, the two caps serve as substrate for the hermetic feedthroughs to enable the device powering and data exchange with the external digital controller implemented on a Field-Programmable Gate Array (FPGA) board. The package has an outer diameter of 7mm and a total length of 26mm. In addition, a humidity and temperature sensor was also included inside the package to allow future hermeticity and life-time estimation tests. Moreover, a wireless, wearable and non-invasive EEG recording system is proposed in order to improve the control over the artificial limb,by integrating the neural signals recorded from the PNS with those directly acquired from the brain. To first investigate the system requirements, a Component-Off-The-Shelf (COTS) device was designed. It includes a low-power 8- channel acquisition module and a Bluetooth (BT) transceiver to transmit the acquired data to a remote platform. It was designed with the aimof creating a cheap and user-friendly system that can be easily interfaced with the nowadays widely spread smartphones or tablets by means of a mobile-based application. The presented system, validated through in-vivo experiments, allows EEG signals recording at different sample rates and with a maximum bandwidth of 524Hz. It was realized on a 19cm2 custom PCB with a maximum power consumption of 270mW

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities