An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

Accepted versio

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Low Power Multi-Channel Interface for Charge Based Tactile Sensors

Analog front end electronics are designed in 65 nm CMOS technology to process charge pulses arriving from a tactile sensor array. This is accomplished through the use of charge sensitive amplifiers and discrete time filters with tunable clock signals located in each of the analog front ends. Sensors were emulated using Gaussian pulses during simulation. The digital side of the system uses SAR (successive approximation register) ADCs for sampling of the processed sensor signals. Adviser: Sina Balkı

An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

Accepted versio

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between -6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

A CMOS Analog Front-End for Tunnelling Magnetoresistive Spintronic Sensing Systems

This paper presents a CMOS readout circuit for an integrated and highly-sensitive tunnel-magnetoresistive (TMR) sensor. Based on the characterization of the TMR sensor in the finite-element simulation, using COMSOL Multiphysics, the circuit including a Wheatstone bridge and an analogue front-end (AFE) circuit, were designed to achieve low-noise and low-power sensing. We present a transimpedance amplifier (TIA) that biases and amplifies a TMR sensor array using switched-capacitors external noise filtering and allows the integration of TMR sensors on CMOS without decreasing the measurement resolution. Designed using TSMC 0.18 μm 1V technology, the amplifier consumes 160 nA at 1.8 V supply to achieve a dc gain of 118 dB and a bandwidth of 3.8 MHz. The results confirm that the full system is able to detect the magnetic field in the pico-Tesla range with low circuit noise (2.297 pA/√Hz) and low power consumption (86 μW). A concurrent reduction in the power consumption and attenuation of noise in TMR sensors makes them suitable for long-term deployment in spintronic sensing systems

A low-power delta-sigma modulator ADC for sensor system applications

This paper discusses a third-order tri-level quantizer delta-sigma modulator analog-digital converter (ADC) for cascaded integrators with distributed feedback (CIFB) and cascaded integrators with distributed feedforward (CIFF) structure for sensor system applications. The signal transfer function (STF) and noise transfer function (NTF) discussed for poles and zeroes. Oversampling ratio (OSR) and different quantizer level presented for the modulator structure to trade-off the targeted bandwidth and complexity of increased quantizer level. NTF zero optimization technique also implemented to further reduce inband quantization noise by shaping at high frequency, which is later filtered by digital low-pass filter. Mismatch simulation results also performed for quantizer levels considering the performance degradation of the modulator. Operational amplifier (op-amp) for the front-end integrator optimized for minimum power consumption by considering low finite DC-gain, limited slew-rate, minimum required gain-bandwidth product (GBW). The proposed model simulations provided and discussed. Non-ideal effect for the proposed complete modulator CIFF structure for switched-capacitor circuit level implementation performed. The non-ideal parameters like thermal noise, sampling jitter, white noise, and switch nonlinearity also discussed. Modeling simulation results for CIFF structure with trilevel quantizer, shows that proposed modulator structure can achieve signal-to-noise ratio (SNR) of 133dB for sensor system bandwidth of 10kHz with OSR = 128