Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field

Recent trends in low-frequency noise reduction techniques for integrated circuits

This paper presents the two main circuit techniques, namely autozeroing (AZ) and chopper stabilization (CS), that are used to reduce the 1/f noise and offset in amplifiers typically used in sensor electronics interfaces. After recalling their main properties, it looks into recent trends in circuit noise reduction techniques. First, the correlated multiple sampling (CMS) technique is presented as a generalization of AZ and correlated double sampling (CDS). Introduced in CMOS image sensors (CIS), it combines noise averaging and canceling and allows to further reduce the 1/f noise, but, like AZ, it is also ultimately limited by the aliasing of the broadband white noise. Another technique combining noise canceling and CS in a transimpedance amplifier (TIA) for bio-sensors is presented. It allows to maintain a low input impedance required by the TIA, while reducing the noise of the main transimpedance stage. CS is then used to cancel the noise of the following stages

Design of A Low-power Precision Op Amp with Ping-pong Autozero Architecture

Precision op amps are widely used in instrumentation, automotive, and industrial applications. This thesis presents the design and characterization of a low-power precision operational amplifier that uses “ping-pong” autozero architecture for automatic offset correction. The op amp is designed for extreme environment applications, operating across a wide temperature range (minus 180 degree Celsius to plus 120 degree Celsius) with low offset, low drift and low power consumption. This design has been fabricated in a SiGe BiCMOS 0.5-micron process and the measured results demonstrate that the op amp is fully functional and achieves less than 40 microvolt input-referred offset voltage with 0.1 microvolt per degree offset voltage drift and 1 microwatt power consumption

A Low Power Low Noise Instrumentation Amplifier For ECG Recording Applications

The instrumentation amplifier (IA) is one of the crucial blocks in an electrocardiogram recording system. It is the first block in the analog front-end chain that processes the ECG signal from the human body and thus it defines some of the most important specifications of the ECG system like the noise and common mode rejection ratio (CMRR). The extremely low ECG signal bandwidth also makes it difficult to achieve a fully integrated system. In this thesis, a fully integrated IA topology is presented that achieves low noise levels and low power dissipation. The chopper stabilized technique is implemented together with an AC coupled amplifier to reduce the effect of flicker noise while eliminating the effect of the differential electrode offset (DEO). An ultra low power operational transconductance amplifier (OTA) is the only active power consuming block in the IA and so an overall low power consumption is achieved. A new implementation of a large resistor using the T-network is presented which makes it easy to achieve a fully integrated solution. The proposed IA operates on a 2V supply and consumes a total current of 1.4µA while achieving an integrated noise of 1.2µVrms within the bandwidth. The proposed IA will relax the power and noise requirements of the analog-to-digital converter (ADC) that immediately follows it in the signal chain and thus reduce the cost and increase the lifetime of the recording device. The proposed IA has been implemented in the ONSEMI 0.5µm CMOS technology

Low-power amplifier chopper stabilization for a digital-to-analog converter

Includes bibliographical references (p. 59).Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Modern portable media devices demand low-power and low-noise performance from the internal digital-to-analog converter. CMOS design has allowed for oversampling sigma-delta modulation to achieve these goals. However, noise is typically limited by the kT/C noise in the switched capacitor filter following the digital modulation. These filters also require a large amount of on-chip capacitance. The goal of this project is to design a continuous-time output stage for a DAC. A continuous-time output requires much less capacitance than the SC filter. Chopper stabilization is applied to the amplifier to reduce the low-frequency noise. The challenge of this architecture is maintaining amplifier harmonic performance and transient performance. In simulations, chopper stabilization improved signal-to-noise ratio by 11dB while maintaining system level harmonic distortion performance.by Keith Jordy.M.Eng

Magnetoresistive biosensors with on-chip pulsed excitation and magnetic correlated double sampling.

Giant magnetoresistive (GMR) sensors have been shown to be among the most sensitive biosensors reported. While high-density and scalable sensor arrays are desirable for achieving multiplex detection, scalability remains challenging because of long data acquisition time using conventional readout methods. In this paper, we present a scalable magnetoresistive biosensor array with an on-chip magnetic field generator and a high-speed data acquisition method. The on-chip field generators enable magnetic correlated double sampling (MCDS) and global chopper stabilization to suppress 1/f noise and offset. A measurement with the proposed system takes only 20 ms, approximately 50× faster than conventional frequency domain analysis. A corresponding time domain temperature correction technique is also presented and shown to be able to remove temperature dependence from the measured signal without extra measurements or reference sensors. Measurements demonstrate detection of magnetic nanoparticles (MNPs) at a signal level as low as 6.92 ppm. The small form factor enables the proposed platform to be portable as well as having high sensitivity and rapid readout, desirable features for next generation diagnostic systems, especially in point-of-care (POC) settings

Integrated system for a high resolution MEMS accelerometer

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 201

Low Power Bio-potential Amplifier (for EEG)

The size and dependency on power supply of current biopotential data acquisition systems prohibit continuous monitoring of biopotential signals through battery powered devices. As the interest in continuous monitoring of EEG increases for healthcare and research purposes such as seizure detection, there is an increasing need to bring down the power consumption on the biopotential amplifier (BPA). BPA is one of the most power consuming components in the biopotential data acquisition system. In this FYP, we will develop a method to improve the existing BPA using MIMOS 0.35um process technology through implementation of various low power flicker noise cancelation techniques. Techniques used include low impedance node chopping and non-overlapping demodulation chopping. The scope of this FYP is focusing on design and simulation on Cadence software in circuit level implementation. This work provides insights as well as a starting point in lowering the power consumption of bio-potential data acquisition system. This will help to enable battery power system for continuous monitoring of EEG signals in the future. This final report discusses on both the literature review, background of the projects and methodology as well as the outcome of the work. The report is concluded by suggesting future works that can be carried out in this final year project (FYP)

A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C