15 research outputs found
Generic vs custom; analogue vs digital: on the implementation of an online EEG signal processing algorithm
Published versio
Ultra low power circuits for a miniature apnoea detection device
Imperial Users onl
Data Conversion Within Energy Constrained Environments
Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings
Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing
Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments
CMOS analog-digital circuit components for low power applications
Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction
circuits for energy harvester.
The main contribution of this work is the realization of low power consumption and
high efficient circuit components employable in a management circuit for piezoelectricbased
energy harvester. This thesis focuses on the development of current references and
operational amplifiers addressing low power demands. A brief literature review is conducted
on the components necessary for the power extraction circuit, including introduction to
CMOS technology design and research of known low power circuits. It is presented with
multiple implementations for voltage and current references, as well for operational amplifier
designs.
A self-biased current reference, capable of driving the remaining harvesting circuit, is
designed and verified. A novel operational amplifier is proposed by the use of a minimum
current selector circuit topology. It is a three-stage amplifier with an AB class output stage,
comprised by a translinear circuit. The circuit is designed, taking into consideration noise
reduction. The circuit components are designed based on the 0.35mm CMOS technology.
A physical layout is developed for fabrication purposes. This technology was chosen with
consideration of robustness, costliness and performance. The current reference is capable of
outputting a stable 12nA current, which may remain stable in a broad range of power supply
voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at
voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW,
with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de
muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração
de energia com base num elemento piezoelétrico.
Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um
amplificador operacional com baixa exigência de consumo. Uma revisão da literatura
é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor
(CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações
de referência de tensão e corrente são consideradas, e amplificadores operacionais também.
Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e
verificada. Um amplificador operacional original é proposto com uma topologia de seleção
de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída
de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na
sua implementação.
Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi
também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em
conta o seu custo versus desempenho.
A referência de corrente produz uma corrente de 12nA, permanecendo estável para
tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um
coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de
alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima
mantida no estágio de saída
ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS
Ph.DDOCTOR OF PHILOSOPH