Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH

Low-pass CMOS Sigma-Delta Converter

A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante. O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução. Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption

Low-voltage Low-power Switched-Capacitor ?S Modulator Design

Ph.DDOCTOR OF PHILOSOPH

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, ‘A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver’, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe

Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs

Navigation/traffic control satellite mission study. Volume 3 - System concepts

Satellite network for air traffic control, solar flare warning, and collision avoidanc