Ring-oscillator with multiple transconductors for linear analog-to-digital conversion

This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.This research was funded by Project TEC2017-82653-R, Spain

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

SMART-E-PTDC/CTM-PAM/04012/2022, IDS-PAPER-PTDC/CTM-PAM/4241/2020 and PEST (CTS/UNINOVA)-UIDB/00066/2020. This work also received funding from the European Community’s H2020 program [Grant Agreement No. 716510 (ERC-2016-StG TREND) and 952169 (SYNERGY, H2020-WIDESPREAD-2020-5, CSA)]. Publisher Copyright: © 2022 by the authors.In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated (Formula presented.) is close to 16.2 fJ/conv.-step.publishersversionpublishe

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

Design of a Comparator and an Amplifier in CMOS using standard logic gates

Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe- sizability, as well as the voltage scalability between technologies. In this work a general pur- pose standard-cell-based voltage comparator and amplifier are presented. The objective is to design a general purpose standard-cell-based comparator and ampli- fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving some of the specifications of the studied topologies. Various simulation testbenches were made to test the studied topologies of comparators and amplifiers, in which the results were compared. The top performing standard-cell com- parator and amplifier were then modified. After successfully designing the comparator, it was used in the design of an opamp-less Sigma-Delta modulator (ΣΔM). The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of 10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz. The proposed amplifier is a single-path three-stage inverter-based operational transcon- ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of 63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW, considering a load of 1 pF. The proposed comparator was employed in the ΣΔM with a standard-cell based edge- triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of 2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple- tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são apresentados um comparador de tensão e um amplificador utilizando portas lógicas. O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por- tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me- lhoramento de algumas das especificações das mesmas. Foram realizados vários bancos de teste para testar as topologias estudadas de compa- radores e amplificadores, em que os resultados foram comparados. As topologias de compa- radores e amplificadores de portas lógicas com melhor performance foram então modificadas. Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula- dor Sigma-Delta (ΣΔM) opamp-less. O comparador proposto é um OR-AND-Inversor com duas entradas e saídas, que apre- senta um atraso de 109 ps, offset estático na entrada de 591 μV, offset aleatório de 10.42 μV, enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz O amplificador proposto é um amplificador operacional de transcondutância single- path three-stage inverter-based com um loop ativo de realimentação do modo-comum, que apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF. O comparador proposto foi aplicado no ΣΔM com um flip-flop edge-triggered baseado em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7 μW

Low-Voltage, Low-Area, nW-Power CMOS Digital-Based Biosignal Amplifier

This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 μVRMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR

Low-voltage, low-area, nW-power CMOS digital-based biosignal amplifier

This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22× times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 μVRMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR

A Novel differential to single-ended converter for ultra-low-voltage inverter-based OTAs

For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a “diode" connected device to implement a voltage gain approximately equal to -1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverterbased D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations.We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint

完全自動合成可能な低電力・広入力統計的フラッシュ型A/D変換回路

This work presents a fully synthesizable stochastic flash A/D converter (SFADC), which can operate at the supply voltage of 0.6V with power consumption as low as 1.5mW at the clock frequency of 250MHz. By employing the all-digital comparator, the SFADC can be described with Verilog netlist and synthesized according to a standard digital design flow. Cross-coupled dynamic comparator structure saves the overall power due to remarkable control of dynamic power consumption. In addition, the rail-to-rail characteristic of comparator and the proposed linearity enhancement technique based on SFADC are proposed, allowing us to design a wide input-range stochastic flash ADC.北九州市立大

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development