Robust Circuit Design for Low-Voltage VLSI.

Voltage scaling is an effective way to reduce the overall power consumption, but the major challenges in low voltage operations include performance degradation and reliability issues due to PVT variations. This dissertation discusses three key circuit components that are critical in low-voltage VLSI. Level converters must be a reliable interface between two voltage domains, but the reduced on/off-current ratio makes it extremely difficult to achieve robust conversions at low voltages. Two static designs are proposed: LC2 adopts a novel pulsed-operation and modulates its pull-up strength depending on its state. A 3-sigma robustness is guaranteed using a current margin plot; SLC inherently reduces the contention by diode-insertion. Improvements in performance, power, and robustness are measured from 130nm CMOS test chips. SRAM is a major bottleneck in voltage-scaling due to its inherent ratioed-bitcell design. The proposed 7T SRAM alleviates the area overhead incurred by 8T bitcells and provides robust operation down to 0.32V in 180nm CMOS test chips with 3.35fW/bit leakage. Auto-Shut-Off provides a 6.8x READ energy reduction, and its innate Quasi-Static READ has been demonstrated which shows a much improved READ error rate. A use of PMOS Pass-Gate improves the half-select robustness by directly modulating the device strength through bitline voltage. Clocked sequential elements, flip-flops in short, are ubiquitous in today’s digital systems. The proposed S2CFF is static, single-phase, contention-free, and has the same number of devices as in TGFF. It shows a 40% power reduction as well as robust low-voltage operations in fabricated 45nm SOI test chips. Its simple hold-time path and the 3.4x improvement in 3-sigma hold-time is presented. A new on-chip flip-flop testing harness is also proposed, and measured hold-time variations of flip-flops are presented.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111525/1/yejoong_1.pd

Wireless power transfer for combined sensing and stimulation in implantable biomedical devices

Actuellement, il existe une forte demande de Headstage et de microsystèmes intégrés implantables pour étudier l’activité cérébrale de souris de laboratoire en mouvement libre. De tels dispositifs peuvent s’interfacer avec le système nerveux central dans les paradigmes électriques et optiques pour stimuler et surveiller les circuits neuronaux, ce qui est essentiel pour découvrir de nouveaux médicaments et thérapies contre des troubles neurologiques comme l’épilepsie, la dépression et la maladie de Parkinson. Puisque les systèmes implantables ne peuvent pas utiliser une batterie ayant une grande capacité en tant que source d’énergie primaire dans des expériences à long terme, la consommation d’énergie du dispositif implantable est l’un des principaux défis de ces conceptions. La première partie de cette recherche comprend notre proposition de la solution pour diminuer la consommation d’énergie des microcircuits implantables. Nous proposons un nouveau circuit de décalage de niveau qui convertit les niveaux de signaux sub-seuils en niveaux ultra-bas à haute vitesse en utilisant une très faible puissance et une petite zone de silicium, ce qui le rend idéal pour les applications de faible puissance. Le circuit proposé introduit une nouvelle topologie de décaleur de niveau de tension utilisant un condensateur de décalage de niveau pour augmenter la plage de tensions de conversion, tout en réduisant considérablement le retard de conversion. Le circuit proposé atteint un délai de propagation plus court et une zone de silicium plus petite pour une fréquence de fonctionnement et une consommation d’énergie donnée par rapport à d’autres solutions de circuit. Les résultats de mesure sont présentés pour le circuit proposé fabriqué dans un processus CMOS TSMC de 0,18- mm. Le circuit présenté peut convertir une large gamme de tensions d’entrée de 330 mV à 1,8 V et fonctionner sur une plage de fréquence de 100 Hz à 100 MHz. Il a un délai de propagation de 29 ns et une consommation d’énergie de 61,5 nW pour les signaux d’entrée de 0,4 V, à une fréquence de 500 kHz, surpassant les conceptions précédentes. La deuxième partie de cette recherche comprend nos systèmes de transfert d’énergie sans fil proposé pour les applications optogénétiques. L’optogénétique est la combinaison de la méthode génétique et optique d’excitation, d’enregistrement et de contrôle des neurones biologiques. Ce système combine plusieurs technologies telles que les MEMS et la microélectronique pour collecter et transmettre les signaux neuronaux et activer un stimulateur optique via une liaison sans fil. Puisque les stimulateurs optiques consomment plus de puissance que les stimulateurs électriques, l’interface utilise la transmission de puissance par induction en utilisant des moyens innovants au lieu de la batterie avec la petite capacité comme source d’énergie.Notre première contribution dans la deuxième partie fournit un système de cage domestique intelligent basé sur des barrettes multi-bobines superposées à travers un récepteur multicellulaire implantable mince de taille 1×1 cm2, implanté sous le cuir chevelu d’une souris de laboratoire, et unité de gestion de l’alimentation intégrée. Ce système inductif est conçu pour fournir jusqu’à 35,5 mW de puissance délivrée à un émetteur-récepteur full duplex de faible puissance entièrement intégré pour prendre en charge des implants neuronaux à haute densité et bidirectionnels. L’émetteur (TX) utilise une bande ultra-large à impulsions radio basée sur des approches de combinaison, et le récepteur (RX) utilise une topologie à bande étroite à incrémentation de 2,4 GHz. L’émetteur-récepteur proposé fournit un débit de données de liaison montante TX à 500 Mbits/s double et un débit de données de liaison descendante RX à 100 Mbits/s, et est entièrement intégré dans un processus CMOS TSMC de 0,18-mm d’une taille totale de 0,8 mm2 . La puissance peut être délivrée à partir d’un signal de porteuse de 13,56-MHz avec une efficacité globale de transfert de puissance supérieure à 5% sur une distance de séparation allant de 3 cm à 5 cm. Notre deuxième contribution dans les systèmes de collecte d’énergie porte sur la conception et la mise en oeuvre d’une cage domestique de transmission de puissance sans fil (WPT) pour une plate-forme de neurosciences entièrement sans fil afin de permettre des expériences optogénétiques ininterrompues avec des rongeurs de laboratoire vivants. La cage domestique WPT utilise un nouveau réseau hybride de transmetteurs de puissance (TX) et des résonateurs multi-bobines segmentés pour atteindre une efficacité de transmission de puissance élevée (PTE) et délivrer une puissance élevée sur des distances aussi élevées que 20 cm. Le récepteur de puissance à bobines multiples (RX) utilise une bobine RX d’un diamètre de 1 cm et une bobine de résonateur d’un diamètre de 1,5 cm. L’efficacité moyenne du transfert de puissance WPT est de 29, 4%, à une distance nominale de 7 cm, pour une fréquence porteuse de 13,56 MHz. Il a des PTE maximum et minimum de 50% et 12% le long de l’axe Z et peut délivrer une puissance constante de 74 mW pour alimenter le headstage neuronal miniature. En outre, un dispositif implantable intégré dans un processus CMOS TSMC de 0,18-mm a été conçu et introduit qui comprend 64 canaux d’enregistrement, 16 canaux de stimulation optique, capteur de température, émetteur-récepteur et unité de gestion de l’alimentation (PMU). Ce circuit est alimenté à l’intérieur de la cage du WPT à l’aide d’une bobine réceptrice d’un diamètre de 1,5 cm pour montrer les performances du circuit PMU. Deux tensions régulées de 1,8 V et 1 V fournissent 79 mW de puissance pour tout le système sur une puce. Notre dernière contribution est un système WPT insensible aux désalignements angulaires pour alimenter un headstage pour des applications optogénétiques qui a été précédemment proposé par le Laboratoire de Microsystèmes Biomédicaux (BioML-UL) à ULAVAL. Ce système est la version étendue de notre deuxième contribution aux systèmes de collecte d’énergie.Dans la version mise à jour, un récepteur de puissance multi-bobines utilise une bobine RX d’un diamètre de 1,0 cm et une nouvelle bobine de résonateur fendu d’un diamètre de 1,5 cm, qui résiste aux défauts d’alignement angulaires. Dans cette version qui utilise une cage d’animal plus petite que la dernière version, 4 résonateurs sont utilisés côté TX. De plus, grâce à la forme et à la position de la bobine de répéteur L3 du côté du récepteur, la liaison résonnante hybride présentée peut correctement alimenter la tête sans interruption causée par le désalignement angulaire dans toute la cage de la maison. Chaque 3 tours du répéteur RX a été enveloppé avec un diamètre de 1,5 cm, sous différents angles par rapport à la bobine réceptrice. Les résultats de mesure montrent un PTE maximum et minimum de 53 % et 15 %. La méthode proposée peut fournir une puissance constante de 82 mW pour alimenter le petit headstage neural pour les applications optogénétiques. De plus, dans cette version, la performance du système est démontrée dans une expérience in-vivo avec une souris ChR2 en mouvement libre qui est la première expérience optogénétique sans fil et sans batterie rapportée avec enregistrement électrophysiologique simultané et stimulation optogénétique. L’activité électrophysiologique a été enregistrée après une stimulation optogénétique dans le Cortex Cingulaire Antérieur (CAC) de la souris.Our first contribution in the second part provides a smart home-cage system based on overlapped multi-coil arrays through a thin implantable multi-coil receiver of 1×1 cm2 of size, implantable bellow the scalp of a laboratory mouse, and integrated power management circuits. This inductive system is designed to deliver up to 35.5 mW of power delivered to a fully-integrated, low-power full-duplex transceiver to support high-density and bidirectional neural implants. The transmitter (TX) uses impulse radio ultra-wideband based on an edge combining approach, and the receiver (RX) uses a 2.4- GHz on-off keying narrow band topology. The proposed transceiver provides dual-band 500-Mbps TX uplink data rate and 100-Mbps RX downlink data rate, and it is fully integrated into 0.18-mm TSMC CMOS process within a total size of 0.8 mm2. The power can be delivered from a 13.56-MHz carrier signal with an overall power transfer efficiency above 5% across a separation distance ranging from 3 cm to 5 cm. Our second contribution in power-harvesting systems deals with designing and implementation of a WPT home-cage for a fully wireless neuroscience platform for enabling uninterrupted optogenetic experiments with live laboratory rodents. The WPT home-cage uses a new hybrid parallel power transmitter (TX) coil array and segmented multi-coil resonators to achieve high power transmission efficiency (PTE) and deliver high power across distances as high as 20 cm. The multi-coil power receiver (RX) uses an RX coil with a diameter of 1 cm and a resonator coil with a diameter of 1.5 cm. The WPT home-cage average power transfer efficiency is 29.4%, at a nominal distance of 7 cm, for a power carrier frequency of 13.56-MHz. It has maximum and minimum PTE of 50% and 12% along the Z axis and can deliver a constant power of 74 mW to supply the miniature neural headstage. Also, an implantable device integrated into a 0.18-mm TSMC CMOS process has been designed and introduced which includes 64 recording channels, 16 optical stimulation channels, temperature sensor, transceiver, and power management unit (PMU). This circuit powered up inside the WPT home-cage using receiver coil with a diameter of 1.5 cm to show the performance of the PMU circuit. Two regulated voltages of 1.8 V and 1 V provide 79 mW of power for all the system on a chip. Our last contribution is an angular misalignment insensitive WPT system to power up a headstage which has been previously proposed by the Biomedical Microsystems Laboratory (BioML-UL) at ULAVAL for optogenetic applications. This system is the extended version of our second contribution in power-harvesting systems. In the updated version a multi-coil power receiver uses an RX coil with a diameter of 1.0 cm and a new split resonator coil with a diameter of 1.5 cm, which is robust against angular misalignment. In this version which is using a smaller animal home-cage than the last version, 4 resonators are used on the TX side. Also, thanks to the shape and position of the repeater coil of L3 on the receiver side, the presented hybrid resonant link can properly power up the headstage without interruption caused by the angular misalignment all over the home-cage. Each 3 turns of the RX repeater has been wrapped up with a diameter of 1.5 cm, in different angles compared to the receiver coil. Measurement results show a maximum and minimum PTE of 53 % and 15 %. The proposed method can deliver a constant power of 82 mW to supply the small neural headstage for the optogenetic applications. Additionally, in this version, the performance of the system is demonstrated within an in-vivo experiment with a freely moving ChR2 mouse which is the first fully wireless and batteryless optogenetic experiment reported with simultaneous electrophysiological recording and optogenetic stimulation. Electrophysiological activity was recorded after delivering optogenetic stimulation in the Anterior Cingulate Cortex (ACC) of the mouse.Currently, there is a high demand for Headstage and implantable integrated microsystems to study the brain activity of freely moving laboratory mice. Such devices can interface with the central nervous system in both electrical and optical paradigms for stimulating and monitoring neural circuits, which is critical to discover new drugs and therapies against neurological disorders like epilepsy, depression, and Parkinson’s disease. Since the implantable systems cannot use a battery with a large capacity as a primary source of energy in long-term experiments, the power consumption of the implantable device is one of the leading challenges of these designs. The first part of this research includes our proposed solution for decreasing the power consumption of the implantable microcircuits. We propose a novel level shifter circuit which converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting capacitor to increase the range of conversion voltages, while significantly reducing the conversion delay. The proposed circuit achieves a shorter propagation delay and a smaller silicon area for a given operating frequency and power consumption compared to other circuit solutions. Measurement results are presented for the proposed circuit fabricated in a 0.18-mm TSMC CMOS process. The presented circuit can convert a wide range of the input voltages from 330 mV to 1.8 V, and operate over a frequency range of 100-Hz to 100-MHz. It has a propagation delay of 29 ns, and power consumption of 61.5 nW for input signals 0.4 V, at a frequency of 500-kHz, outperforming previous designs. The second part of this research includes our proposed wireless power transfer systems for optogenetic applications. Optogenetics is the combination of the genetic and optical method of excitation, recording, and control of the biological neurons. This system combines multiple technologies such as MEMS and microelectronics to collect and transmit the neuronal signals and to activate an optical stimulator through a wireless link. Since optical stimulators consume more power than electrical stimulators, the interface employs induction power transmission using innovative means instead of the battery with the small capacity as a power source

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range

Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques

The internet-of-things is a growing market segment which is based on an arrayof portable communication devices with high power efficiency. Advanced semiconductortechnology can easily improve their digital performance, but the samecannot be said for the analog blocks which are vital to their operation. Highperformance analog circuits continue to use conventional design techniques andarchitectures at the expense of power efficiency. Deeply scaled CMOS exaggeratesthis trade-off, opening the door for novel system techniques that take advantage ofthe digital nature of sub-micron transistors. This research focuses on two highlydigital ADCs which can mitigate the short channel effects of limited output swingand low intrinsic gain while also benefiting from process scaling.First, a multi-domain ADC is used to perform quantization on both voltageand time domain signals, relaxing the power-performance trade-off. This hybridapproach can lead to a high resolution, high efficiency data converter in scaledprocess. A prototype ADC was fabricated in 180nm CMOS, showing an SNDRof 73 dB, operating at 20 MHz sampling frequency, with a power consumption of1.28 mW.Next, an automated synthesis process is used to automatically generate a highspeed VCO-based quantizer from verilog code. Stochastic spatial averaging iscombined with a high speed open-loop noise-shaping quantizer to provide enhancedresolution in the presence of device mismatch. Simulation results of a prototypeADC in 180nm CMOS shows an SNDR of 49 dB, operating at 800 MHz samplingfrequency and 50 MHz signal bandwidth.Keywords: data converter, synthesis, verilog, ADC, SAR, TD

Ultra Low Power Digital Circuit Design for Wireless Sensor Network Applications

Ny forskning innenfor feltet trådløse sensornettverk åpner for nye og innovative produkter og løsninger. Biomedisinske anvendelser er blant områdene med størst potensial og det investeres i dag betydelige beløp for å bruke denne teknologien for å gjøre medisinsk diagnostikk mer effektiv samtidig som man åpner for fjerndiagnostikk basert på trådløse sensornoder integrert i et ”helsenett”. Målet er å forbedre tjenestekvalitet og redusere kostnader samtidig som brukerne skal oppleve forbedret livskvalitet som følge av økt trygghet og mulighet for å tilbringe mest mulig tid i eget hjem og unngå unødvendige sykehusbesøk og innleggelser. For å gjøre dette til en realitet er man avhengige av sensorelektronikk som bruker minst mulig energi slik at man oppnår tilstrekkelig batterilevetid selv med veldig små batterier. I sin avhandling ” Ultra Low power Digital Circuit Design for Wireless Sensor Network Applications” har PhD-kandidat Farshad Moradi fokusert på nye løsninger innenfor konstruksjon av energigjerrig digital kretselektronikk. Avhandlingen presenterer nye løsninger både innenfor aritmetiske og kombinatoriske kretser, samtidig som den studerer nye statiske minneelementer (SRAM) og alternative minnearkitekturer. Den ser også på utfordringene som oppstår når silisiumteknologien nedskaleres i takt med mikroprosessorutviklingen og foreslår løsninger som bidrar til å gjøre kretsløsninger mer robuste og skalerbare i forhold til denne utviklingen. De viktigste konklusjonene av arbeidet er at man ved å introdusere nye konstruksjonsteknikker både er i stand til å redusere energiforbruket samtidig som robusthet og teknologiskalerbarhet øker. Forskningen har vært utført i samarbeid med Purdue University og vært finansiert av Norges Forskningsråd gjennom FRINATprosjektet ”Micropower Sensor Interface in Nanometer CMOS Technology”

A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor

10.1109/ASSCC.2014.7008920Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014301-30

CMOS Integrated Circuits for RF-powered Wireless Temperature Sensor

This dissertation presents original research contributions in the form of twelve scientific publications that represent advances related to RF-to-DC converters, reference circuits (voltage, current and frequency) and temperature sensors. The primary focus of this research was to design efficient and low power CMOS-based circuit components, which are useful in various blocks of an RF-powered wireless sensor node.  The RF-to-DC converter or rectifier converts RF energy into DC energy, which is utilized by the sensor node. In the implementation of a CMOS-based RF-to-DC converter, the threshold voltage of MOS transistors mainly affects the conversion efficiency. Hence, for the first part of this research, different threshold voltage compensation schemes were developed for the rectifiers. These schemes were divided into two parts; first, the use of the MOSFET body terminal biasing technique and second, the use of an auxiliary circuit to obtain threshold voltage compensation. In addition to these schemes, the use of an alternate signaling scheme for voltage multiplier configuration of differential input RF-harvesters has also been investigated.  A known absolute value of voltage or current is the most useful for an integrated circuit. Thus, the circuit which generates the absolute value of voltage or current is cited as the voltage or current reference circuit respectively. Hence, in the second part of the research, simple, low power and moderately accurate, voltage and current reference circuits were developed for the power management unit of the sensor node. Besides voltage and current reference circuits, a frequency reference circuit was also designed. The use of the frequency reference circuit is in the digital processing and timing functions of the sensor node.  In the final part of the research, temperature sensing was selected as an application for the sensor node. Here, voltage and current based sensor cores were developed to sense the temperature. A smart temperature sensor was designed by using the voltage cores to obtain temperature information in terms of the duty-cycle. Similarly, the temperature equivalent current was converted into the frequency to obtain a temperature equivalent output signal.  All these implementations were done by using two integrated circuits which were fabricated during the year 2013-14.

Interface Engineering to Control Charge Transport in Colloidal Semiconductor Nanowires and Nanocrystals

Colloidal semiconductor nanocrystals (NCs) are a class of materials that has rapidly gained prominence and has shown the potential for large area electronics. These materials can be synthesized cheaply and easily made in high quality, with tunable electronic properties. However, evaluating if colloidal nanostructures can be used as a viable semiconducting material for large area electronics and more complex integrated circuits has been a long standing question in the field. When these materials are integrated into solid-state electronics, multiple interfaces need to be carefully considered to control charge transport, these interfaces are the: metal contact/semiconductor, dielectric/semiconductor and the nanocrystal surface. Here, we use colloidal nanowire (NW) field-effect transistors (FETs) as a model system to understand doping and hysteresis. Through controllable doping, we fabricated PbSe NW inverters that exhibit amplification and demonstrate that these nanostructured materials could be used in more complex integrated circuits. By manipulating the dielectric interface, we are able to reduce the hysteresis and make low-voltage, low-hysteresis PbSe NW FETs on flexible plastic, showing the promise of colloidal nanostructures in large area flexible electronics. In collaboration, we are able to fabricate high-performance CdSe NC FETs through the use of a novel ligand, ammonium thiocyanate to enhance electronic coupling, and extrinsic atom in indium to dope and passivate surface traps, to yield mobilities exceeding 15 cm2V-1s-1. Combining high-mobility CdSe NC FETs with our low-voltage plastic platform, we were able to translate the exceptional devices performances on flexible substrates. This enables us to construct, for the first time, nanocrystal integrated circuits (NCICs) constructed from multiple well-behaved, high-performance NC-FETs. These transistors operate with small variations in device parameters over large area in concert, enabling us to fabricate NCIC inverters, amplifiers and ring oscillators. Device performance is comparable to other emerging solution-processable materials, demonstrating that this class of colloidal NCs as a viable semiconducting material for large area electronic applications

Nanoscale Semiconductor Materials and Devices Employing Hybrid 1D and 2D Structures for Tunable Electronic and Photonic Applications

Das, Suprem R. Ph.D., Purdue University, December 2013. Nanoscale Semiconductor Materials and Devices employing Hybrid 1D and 2D structures for Tunable Electronic and Photonic Applications. Major Professor: Dr. David B. Janes. Continued miniaturization of microelectronic devices over past decades has brought the device feature size towards the physical limit. Likewise, enormous `waste energy\u27 in the form of self-heating in almost all of the electronic and optoelectronic devices needs an `energy-efficient low power\u27 and `high performance\u27 material as well as device with alternate geometry. III-V semiconductors are proven to be one of the alternate systems of materials for various applications including CMOS devices, low power and high performance transistor devices, power transistors, as well as thermoelectric applications. InSb, being the bulk semiconductor with lowest bandgap, highest mobility, low effective mass, and highest spin–orbit coupling has potential of providing numerous novel applications. Also, InSb in nanowire form has not been explored in many aspects. First part of this thesis explores the possibility of growing InSb nanowires using solution based electrodeposition technique followed by field effect transistor studies. InSb nanowires have recently shown very promising magneto-transport properties at low temperatures and with magnetic field due to its high spin orbit coupling. This thesis demonstrates initial low temperature device studies on hybrid devices with InSb channel and superconducting electrodes (aluminum). In the last section of InSb nanowire studies, the thesis explores hierarchial branched nanowires with different diameters that demonstrate near unity optical absorption in UV–VIS regime and wavelength dependent absorption in near infrared (NIR) regime. A photonic coupling model was developed to explain the phenomena. The unique photonic properties of the structurally tailored branched nanowire arrays could be used to devise new types of photonic, optoelectronics and/or photovoltaic devices. The second half of the thesis explores another class of hybrid material structure involving 2D semiconductor/semimetal ‘Graphene’ and 1D silver nanowires. While the ultimate goal was to push the limit of ‘transparent and flexible technology’ the thesis, also critically explores the physics of percolation doping to beat the conduction–transparency bottleneck. The thesis demonstrates theory of ‘co-percolation’ involving two individual networks in which the invidual\u27s weakness is circumvented by the other. This study not only applies to the particular system chosen but also could be readily applied to any large scale 2D–1D nanoscale systems such as layered semiconductors, topological insulators and nanowires