A 10b SAR ADC with an Ultra-Low Power Supply

A 0.2V 10-bit 5 kS/s Successive Approximation Register ADC design is presented. This design achieves a very low power consumption due to the ultra-low power supply voltage used. Different aspects in the ADC design are optimized for 0.2V and modified to meet the speed requirements for the ADC. Preliminary Cadence simulations show a 4nW total power consumption with a peak SNDR of 57 dB and a FOM of 1.3 fJ/conversion-step

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s time domain ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply, unique challenges arise that are met with innovation in the sample switch and the quantizer design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s Successive Approximation Register ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply unique challenges arise that are met with innovation in the sample switch and comparator design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

A 10-bit SAR ADC with an Ultra-Low Power Supply

This paper presents a successive approximation analog-to-digital converter (SAR ADC) design, which operates with a 0.2 V power supply. The design utilizes a dynamic bulk biasing scheme to dynamically adjust the relative NMOS and PMOS strengths, which are very sensitive to temperature, process, and mismatch variations at low supply voltages. The design achieves a very low power consumption due to the 0.2 V supply. Several circuits in the design are optimized for full functionality at 0.2 V. Extracted simulations show a total power consumption of 9 nW with a peak SNDR of 61.3 dB and a Walden Figure of Merit of 1.91 fJ/conversion-step

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR