A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Electrical chip-to-chip interconnects suffer from considerable intersymbol interference at multi-Gb/s data rates, due to the frequency-dependent attenuation. Hence, reliable communication at high data rates requires equalization, to compensate for the channel response. As these interconnects are prone to manufacturing tolerances, the equalizer must be adjusted to each specific channel realization to perform optimally. We adopt a reduced-complexity equalization scheme where (part of) the equalizer is fixed, by involving the channel statistics into the equalizer derivation. For a 10 cm on-board microstrip interconnect with a 10% tolerance on its parameters, we point out that 2-PAM transmission using a fixed prefilter and an adjustable feedback filter, both with few taps, yields only a moderate bit error rate degradation, compared to the all-adjustable equalizer; at a bit error rate of 1e-12 these degradations are about 1.1  dB and 3  dB, when operating at 20 Gb/s and 80 Gb/s, respectively

Technological University in 1984 and 1988, respectively

Abstract We present an analysis comparing multi-level signaling to standard NRZ signaling for module-to-module on-board electrical interconnects. To study on-board electrical performance, duobinary and PAM4 I/O models were created and compared to NRZ signaling in behavioral link-level simulations. A great variety of high-density, high-speed on-board module-to-module electrical links were analyzed, and specific interconnect channels were validated experimentally with programmable equalization transceiver chips communicating through a set of fabricated test structures. Link performance was measured with on-chip eye monitoring circuits and an oscilloscope. Simulation results show that NRZ signaling with FFE and DFE equalization offers the best electrical performance

PAM4-바이너리 브리지 칩용 PAM4 트랜스미터 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.고성능 컴퓨팅 시스템, 대용량의 데이터 센터, AI 기술의 발전으로 인해 유선 통신의 대역폭 요구 수준은 기하급수적으로 증가하고 있다. 그러나 I/O 회로의 핀당 대역폭의 향상은 통신 채널의 다양한 한계로 인해 어려움을 겪고 있다. 이는 차세대 DRAM 분야에서도 예외는 아니다. 핀당 데이터 전송 속도를 증가시키는 연구 방향에서는 어느 정도 한계에 봉착하면서 최근에는 High Bandwidth Memory (HBM)와 같이 핀의 개수를 급격히 늘려서 대역폭을 증가시키는 기술도 발전하고 있다. 다른 접근 방식 중 한가지가 다중 레벨 신호 방식이다. 기존의 Non-Return-to-Zero (NRZ) 신호 대신에 다중 레벨 신호 방식을 이용하면 동일한 Nyquist 주파수에서 데이터 속도를 높일 수 있고 이는 DRAM의 차세대 고대역폭 I/O 인터페이스에 좋은 솔루션이 될 수 있으며 현재까지는 4레벨 펄스 진폭 변조 방식 (PAM-4)이 널리 채택되어 있다. 하지만 현재 PAM-4 방식 DRAM이 양산 단계가 아니기 때문에 PAM-4 전용 Memory Tester가 없는 상황이다. 본 논문에서는 차세대 메모리 테스트를 위한 32 Gb/s PAM4 바이너리 브리지에서의 트랜스미터를 제안한다. NRZ 테스터에서 브리지로 전송된 저속 데이터는 고속 PAM4 데이터로 변환되어 메모리로 전달된다. 접지 종단 PAM4 드라이버는 2-탭 피드포워드 이퀄라이저로 출력 전류를 제어하여 0.95의 레벨 불일치 비율 (RLM)을 달성함으로써 단일 종단 출력을 제공한다. 40 nm CMOS 기술로 제작된 브리지 트랜스미터는 0.57 mm2의 활성 영역을 차지하고 102.1 mW의 전력을 소모한다.With the advancement of high-performance computing systems, large-capacity data centers, and AI technologies, the level of bandwidth demand for wired communication is increasing exponentially. However, the improvement of the bandwidth per pin in the I/O circuit compared to the required bandwidth level is difficult due to various limitations of the transmission channel. This is no exception in the next generation of DRAM. While facing limitations from the perspective of research that increases data transmission speed per pin, technologies that increase I/O bandwidth by rapidly increasing the number of pins, such as High Bandwidth Memory (HBM), have also recently developed. One of the other approaches is a multi-level signaling method. Using a multi-level signaling method instead of a conventional Non-Return-to-Zero (NRZ) signal can increase data speed at the same Nyquist frequency, which can be a good solution for the next-generation high-bandwidth I/O interface of DRAM, and so far, a four-level Pulse Amplitude Modulation (PAM-4) has been widely adopted. However, since PAM4 DRAM is not in the mass production stage yet, there is no memory tester dedicated to PAM4 signaling. This paper proposes a transmitter block on a 32 Gb/s PAM4 binary bridge for next-generation memory testing. The low-speed data transmitted from the NRZ tester to the bridge is converted into high-speed PAM4 data through half-rate clock control and transferred to the memory. The ground termination PAM4 driver provides a single-ended output by controlling the output current with a two-tap feed forward equalizer to achieve a Level separation Mismatch Ratio (RLM) of 0.95. Bridge transmitter manufactured with 40 nm CMOS technology occupies an active area of 0.57 mm2 and consumes 102.1 mW of power.ABSTRACT I CONTENTS Ⅲ LIST OF FIGURES Ⅴ LIST OF TABLES Ⅶ CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 BASIC OF MULTI LEVEL SIGNALING 7 2.3 NECESSITY OF PAM4-BINARY BRIDGE 11 CHAPTER 3 DESIGN OF PAM4 TRANSMITTER FOR PAM4-BINARY BRIDGE 14 3.1 DESIGN CONSIDERATION 14 3.2 OVERALL ARCHITECTURE 17 3.3 CIRCUIT IMPLEMENTATION 19 3.3.1 CLOCK GENERATOR 19 3.3.2 PARALLEL PRBS GENERATOR 23 3.3.3 DATA ALIGN / GRAY CODE ENDCODER 26 3.3.4 FFE CONTROL/ SERIALIZER 30 3.3.5 PAM4 DRIVER 33 CHAPTER 4 MEASUREMENT RESULTS 38 4.1 CHIP PHOTOMICROGRAPH 38 4.2 MEASUREMENT SETUP 39 4.3 MEASUREMENT RESULTS 40 4.4 PERFORMANCE SUMMARY 42 CHAPTER 5 CONCLUSION 46 BIBLIOGRAPHY 47 초 록 50석

Feed Forward Equalization Simulation Model for High-Speed Channel Applications

Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2016.This thesis describes the development of simulation models of FFE stages (Feed Forward Equalizer) in transmitters for high-speed channel analysis. The implementation of this equalizer was performed using two different tools: ADS (Advance Design System) by Keysight, which is a commercial tool and SPITDS (Signal and Power Integrity Time Domain Simulator), which is a simulator developed by the Institute of Electromagnetic Theory at the Technical University of Hamburg in Germany. Additionally, the LMS (Least Mean Square) algorithm was implemented in MATLAB and ADS to adjust the equalizer coefficients, in order to have a better signal recovery. Different channels were designed to make comparisons and verify the performance of different implementations of FFE with LMS. Both implementations of the Feed Forward Equalizer and LMS algorithm worked properly, which allows the application of the equalization FFE and the calculation of the equalizer coefficients for signal integrity analysis

State of the art in chip-to-chip interconnects

This thesis presents a study of short-range links for chips mounted in the same package, on printed circuit boards or interposers. Implemented in CMOS technology between 7 and 250 nm, with links that operate at a data rate between 0,4 and 112 Gb/s/pin and with energy efficiencies from 0,3 to 67,7 pJ/bit. The links operate on channels with an attenuation lower than 50 dB. A comparison is made with graphical representations between the different articles that shows the correlation between the different essential metrics of chip-to-chip interconnects, as well as its evolution over the last 20 years.Esta tesis presenta un estudio de enlaces de corto alcance para chips montados en un mismo paquete, en placas de circuito impreso o intercaladores. Implementado en tecnología CMOS entre 7 y 250 nm, con enlaces que operan a una velocidad de datos entre 0,4 y 112 Gb/s/pin y con eficiencias energéticas de 0,3 a 67,7 pJ/bit. Los enlaces operan en canales con una atenuación inferior a 50 dB. Se realiza una comparación con representaciones gráficas entre los diferentes artículos que muestra la correlación entre las distintas métricas esenciales de las interconexiones chip a chip, así como su evolución en los últimos 20 años.Aquesta tesi presenta un estudi d'enllaços de curt abast per a xips muntats en el mateix paquet, en plaques de circuits impresos o interposers. Implementat en tecnologia CMOS entre 7 i 250 nm, amb enllaços que funcionen a una velocitat de dades entre 0,4 i 112 Gb/s/pin i amb eficiències energètiques de 0,3 a 67,7 pJ/bit. Els enllaços funcionen en canals amb una atenuació inferior a 50 dB. Es fa una comparació amb representacions gràfiques entre els diferents articles que mostra la correlació entre les diferents mètriques essencials d'interconnexions xip a xip, així com la seva evolució en els darrers 20 anys

LPDDR5의 외장 자가 테스트를 위한 고속 송신기의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.To overcome the speed gap between Automatic Test Equipment (ATE) and memory, the concept of Built-out Self-test (BOST) was introduced. This thesis presents the design of a transmitter for BOST of LPDDR5. It transmits high-speed DQS and WCK to DRAM while receiving low-speed clocks from ATE. Since they don’t always have clock-toggle, a digital block generates some data patterns. Also, by phase interpolators, phases of the outputs are shifted by desired. The analog part of the transmitter consists of phase interpolators, serializers, and drivers. Phase interpolators and drivers are designed in a current mode to be resistant to supply noise. The divider of the serializer is newly proposed so that the timings of all outputs are the same. In addition, the time it takes to receive enabling signals from ATE and transmit outputs to DRAM is constant. As a result, the transmitter sends DQS and WCK with data patterns to DRAM at the desired timing. The proposed transmitter is fabricated in a 40 nm CMOS process. 1 TX lane consumes 31.4 mW and occupies 0.06 mm2. Measured DQS has a swing of 230 mV and an RMS jitter of 770 fs at 10 Gb/s with 50 Ω termination. And WCK has a swing of 185 mV and an RMS jitter of 894 fs at 10 Gb/s with 40 Ω termination.자동 테스트 장비 (ATE)와 메모리 간의 속도 차이를 극복하기 위해 외장 자가 테스트 (BOST) 개념이 도입되었다. 본 논문은 LPDDR5의 BOST를 위한 송신기 설계를 제시한다. 송신기는 ATE에서 저속 클럭을 받아서 고속 DQS와 WCK를 DRAM에 전송한다. 출력에 항상 클럭 토글만 있는 것은 아니므로 데이터 패턴이 디지털 블록에서 생성된다. 또한 위상 보간기로 출력의 위상을 원하는 대로 움직인다. 송신기의 아날로그 부분은 위상 보간기, 시리얼라이저, 드라이버로 구성된다. 위상 보간기와 드라이버는 공급 노이즈에 견고하도록 전류 모드로 설계되었다. 시리얼라이저의 디바이더가 새롭게 제안되어서 모든 출력의 타이밍이 같다. 또한 ATE에서 활성화 신호를 받아서 DRAM으로 출력을 전송하는데 걸리는 시간도 일정하다. 그 결과 송신기는 데이터 패턴이 있는 DQS와 WCK를 원하는 타이밍에 DRAM으로 전송한다. 제안된 송신기는 40 nm CMOS 공정으로 제작되었다. 송신기의 하나의 레인은 31.4 mW를 소비하고 0.06mm2를 차지한다. 측정된 DQS는 50 Ω 터미네이션일 때 10 Gb/s에서 230 mV의 스윙과 770 fs의 RMS 지터를 가진다. 그리고 WCK는 40 Ω 터미네이션일 때 10 Gb/s에서 185 mV의 스윙과 894 fs의 RMS 지터를 갖는다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON SERIAL LINK 4 2.1 OVERVIEW 4 2.2 BASIS OF MEMORY INTERFACE 7 2.3 BUILDING BLOCKS 9 2.3.1 PHASE INTERPOLATOR 9 2.3.2 SERIALIZER 14 2.3.3 DRIVER 18 CHAPTER 3 DESIGN OF TRANSMITTER FOR BOST 22 3.1 DESIGN CONSIDERATION 22 3.2 OVERALL ARCHITECTURE 24 3.3 CIRCUIT IMPLEMENTATION 26 3.3.1 CLOCK PATH 26 3.3.2 PHASE INTERPOLATOR 29 3.3.3 SERIALIZER 33 3.3.4 DRIVER 41 CHAPTER 4 MEASUREMENTS RESULTS 48 4.1 DIE PHOTOMICROGRAPH 48 4.2 MEASUREMENT SETUP 49 4.3 MEASUREMENT RESULTS 51 4.4 PERFORMANCE SUMMARY 57 CHAPTER 5 CONCLUSION 59 BIBLIOGRAPHY 60 초 록 63석

Techniques for improving timing accuracy of multi-gigahertz track/hold circuits

Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result in harmonic distortions at the output. For different architectures of the T/H circuits, the timing error can arise from the clock random jitter or the phase skew among multi-phase clocks. For the ADC with global T/H circuits in front-end, an architecture with sine-wave sampling clock will be introduced that exhibits less random aperture jitter. First, the signal-dependent sampling error will be analyzed, and the comparison of the calculated and simulated results will be presented. Second, using the signal-to-distortion-ratio (SDR) simulations of a high speed NMOS T/H circuits with varying transition times of the sampling clock, we can compare the effects of the signal-dependent nonlinearity with other non-ideal effects. Based on the above analysis, a new architecture for multi-gigahertz sampling rate ADC using sine wave sampling will be introduced. For the ADC with time-interleaved T/Hs, a histogram based phase detector will be introduced to detect and calibrate the static timing error among the multi-channels. First, different timing error sources in high speed time-interleaved T/H will be analyzed. Second, a histogram based timing error detector will be proposed which not only cancels the skew in the multi-phase clocks but also the mismatch among different interleaved channels of the T/H circuits. An 8-channel 10GS/s T/H with timing error calibration has been implemented using IBM 90nm CMOS process. The static timing error before and after timing calibration will be presented from the measurement results

Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies

Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies. The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER. Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications

Highly digital power efficient techniques for serial links

Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques