High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers

We develop a custom Bit Error Rate test bench based on Altera’s Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-tozero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup

Design of a High Speed Serializer, Timing Analysis and Optimization in TSMC 28nm Process Technology

The use of serializers and deserializers in SerDes devices is a compulsory requirement for chip to chip communication. They are useful in converting parallel to serial data and vice-versa. Mutltiple SerDes devices are housed in a single package. In this paper, a high speed serializer targeted for speeds as high as 20Gbps is proposed and implemented. This is designed primarily for SerDes devices for chip to chip communication. The serializer is designed to facilitate high speed transfer data rates. This design employs differential logic implementation for the circuit, so as to owe high speed operation when compared to single ended implementation. The custom circuit design simulations are compared against standard library files generated by LIBERATE tool. Also Timing fixes were done using Synthesis flow by writing the RTL code for custom top module design and feeding it to DC and IC Compilers. DOI: 10.17762/ijritcc2321-8169.150513

Design Techniques for On-Chip Global Signaling Over Lossy Transmission Lines.

This thesis describes techniques for global high-speed signaling over long (~10mm) lossy chip-serial transmission lines. With the increase in clock frequencies to multi-GHz rates, it has become impossible to move data across a die in a single clock cycle using conventional parallel bus-based communication. There are also reliability problems due to timing errors, skew, and jitter in fully synchronous systems. Noise, coupling, and inductive effects become significant for both intermediate length and global routing. A new on-chip lossy transmission line technique is developed and new driver and receiver circuitry for on-chip serial links are described. High-speed long-range serial signaling is best done over transmission lines. However, because of the relatively high sheet resistance of metal interconnect layers, on-chip transmission lines tend to be lossy. Matched termination with resistors and the proper selection of the characteristic impedance of the transmission line structure can effectively suppress ISI. Fast digital CMOS technology allows pulsed mode data drivers to operate at multi-GHz rates. A phase-tuned receiver samples and de-serializes the received signal. Since the sampling instant is tuned to match the received signal eye, there is no requirement to match the clock and signal routing or clock and signal delays. A complete self-testing on-chip transceiver communicating over a 5.8mm on-chip transmission line is implemented in 0.13um CMOS and tested. The measured BER at 9Gbps is less than 10^-10. Interleaving is usually necessary in high serial data rate serializer and de-serializer circuits. Multi-stage LC oscillators can be used to generate low phase noise multi-phases clocks required for interleaving. Conventional coupling between oscillators introduces out of phase currents, and this out of phase current causes a lower effective quality factor for each oscillator stage. However, capacitive coupling, a new technique, introduces in phase coupling between stages. Increased coupling with a ring of capacitors decreases phase spacing error dramatically and, in addition, the phase noise of multi-stages is also decreased thanks to in-phase coupling.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58491/1/parkjy_1.pd

Design techniques for clocking high performance signaling systems

Scaling of CMOS technology has progressed relentlessly for the past several decades. In order for this unprecedented scaling to benefit the performance of large digital systems, the communication bandwidth between integrated circuits (ICs) must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major bottleneck in overall system performance. In addition, supply voltage scaling, increasing device leakage, and increased noise make existing signaling circuits inefficient and difficult to scale. In this thesis, both analog and digital enhancement techniques to mitigate scaling related issues and improve the performance of building blocks used in high- speed signaling systems are discussed. A digital-to-phase converter (DPC) with a resolution better than 100 femto-second resolution, a hybrid analog/digital clock and data recovery (CDR) architecture that improves the tracking range of tra- ditional CDRs by an order of magnitude, and a digital CDR architecture that obviates the need for the charge pump and the large area occupying loop filter, while achieving error-free operation are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.Keywords: CDR, PL

Realization and Formal Analysis of Asynchronous Pulse Communication Circuits

This work presents an approach to constructing asynchronous pulsed communication circuits. These circuits use small delay elements to introduce a gate level sense of time, removing the need for either a clock or handshaking signal to be part of a high-speed communication link. This construction method allows the creation of links with better than normal jitter tolerance, allowing for simple circuit architectures that can easily be made robust to radiation induced soft error. A 5Gbps radiation-hardened link, targeted at use in detector modules at the LHC, will be presented. This application presents a special challenge due to both very high radiation levels (1+MGy life time dose) and the demand for minimum resource (area, power, cable cost) use. The presented link, realized in 130nm technology, is unique in that it has low power (~50mW end to end) and very low area 0.12mm^2 including electrostatic discharge protection, and I/O amplifiers. Due to its asynchronous construction and the gate design style, the link has essentially zero power dissipation when idle, and enters and exits its idle state with no delay. In addition to the construction of the link, this presentation covers the design and analysis methodology that can be used to create other asynchronous communication circuits. The methodology achieves higher performance than conventional static technology but needs only a reasonable design effort using tools and strategies that are only mildly extended versions of those familiar to digital static designers. It is used to construct the serializer, deserializer, and self-test circuitry for the presented link. In this case, a 5Gbps SER/DES and a 2GHz parallel pseudo-random number generator are implemented in 130nm CMOS technology using a gate design style that does not dissipate static power

Stressed-eye analysis and jitter separation for high-speed serial links

As the computer and electronics industry moves towards higher data rates, the most important concern in the field of signal integrity is jitter. A data communication link path often consists of a transmitter, a channel, and a receiver. Many mechanisms can contribute to jitter, a timing uncertainty in the received signal. For example, transmitters have intrinsic noise sources that contribute to random jitter and to certain types of deterministic jitter. In addition, external coupling may cause periodic jitter. The bandwidth limitation of the channel also contributes to a fourth type of jitter, inter-symbol interference. This thesis studies the various components of jitter and uses mathematical models of them to simulate an actual transmitter. These models allow the injection of various jitter components for stressed-eye testing. To understand the sources of jitter in a received signal, this work studies the manifestation of each jitter component in the time-interval error spectrum is studied and develops procedures to separate the jitter components. These jitter decomposition procedures are compared and validated with real-time and sampling scopes. Bathtub curves and jitter transfer functions were also calculated to facilitate high-speed link path designs. Based on the link-path and jitter analysis algorithms developed here, a cable certification tool was also designed to certify the small form factor pluggable copper cable assemblies against SFF-8431 specifications. This project implemented the framework of the certification tool --Abstract, page iii

Modelização em MatLab® de interfaces de comunicação de alto débito

Mestrado em Engenharia Electrónica e TelecomunicaçõesNow-a-days, high-speed digital data transmission is under continuous development. The constant increasing on the bitrates has been lead to the need of more sophisticated and complex receivers, systems that provide the recovering of the transmitted data over a dispersive channel that degrades the transmitted signal quality. Therefore, the receiver shall compensate the distortion introduced by the channel as well as synchronize the received signal that in addition to distortion, is also affected by jitter. The distortion derived from the channel is attenuated by means of equalization circuits that offset the channel frequency response at the transmission rate, making it as flat as possible for the desired frequency. On the other hand, the synchronization of the received signal is achieved by means of clock and data recovery circuits that usually recover the clock signal through the data transitions for sampling the received data. The main focus of this thesis concerns the modeling of a data receiver for a high-speed interface. The simulation of the data receiver block implies the modeling of a transmission channel depending on its characteristics. The proposed transmission system, from the transmitter to the output of the data recovery block, includes equalization filters for signal conditioning, of which several distinct architectures are studied. It’s proposed two architectures for the clock and data recovery circuit. The first one is a 2x oversampling clock and data recovery circuit based on a Phase Tracking architecture. The second one, is a 3x oversampling clock and data recovery based on a Blind Sampling architecture. By modeling both of the architectures of the clock and data recovery circuit, it’s intended to analyze the respective jitter tolerance results. It is crucial to know the amount of jitter that can be tolerated by these circuits in order to recover the data with a satisfying bit error ratio. The obtained results show a very close match to the theoretical values, where the 2x and 3x oversampling architecture presents a jitter tolerance of, approximately, 12UI and 23UI respectively for low jitter frequencies.Hoje em dia, a transmissão de dados digital de alto débito binário encontra-se em constante evolução. O contínuo aumento das taxas de transmissão tem vindo a exigir sistemas de receção cada vez mais sofisticados e complexos, que facultem a recuperação dos dados transmitidos ao longo de um canal dispersivo que degrada a qualidade do sinal transmitido. Consequentemente, cabe ao recetor compensar a distorção introduzida pelo canal bem como a sincronização do sinal recebido que, para além de sofrer distorção, vem também afetado por jitter. A distorção introduzida pelo canal é atenuada através de circuitos de igualização, que compensam a resposta em frequência do canal à frequência de transmissão, de maneira a tornar a mesma o mais plana possível para a frequência desejada. Por sua vez, a sincronização do sinal recebido é conseguida através de circuitos de recuperação de dados e relógio, que, geralmente, geram um sinal de relógio a partir das transições do sinal de dados que é posteriormente utilizado para fazer a amostragem dos dados recebidos. O principal foco desta tese incide na modelação de um sistema de receção de dados de uma interface de alta velocidade. A simulação do bloco de receção de dados implica a modelação de um canal de transmissão em função das características do mesmo. O sistema de transmissão proposto, desde o transmissor até à saída do bloco de recuperação de dados, inclui filtros de igualização para acondicionamento de sinal, dos quais várias arquiteturas distintas são estudadas. São propostas duas arquiteturas para o circuito de recuperação de dados e relógio. A primeira trata-se de um circuito de recuperação de dados e relógio com sobre-amostragem 2x, baseado numa arquitetura de Phase Tracking. A segunda arquitetura trata-se de um circuito de recuperação de dados e relógio com sobre-amostragem 3x, baseado num arquitetura Blind Sampling. A análise de resultados da modelação de ambas as arquiteturas do circuito de recuperação de dados e relógio é realizada através da aquisição das respetivas curvas de tolerância de jitter. É fundamental conhecer a quantidade de jitter tolerado por estes circuitos a fim de recuperar os dados com uma probabilidade de erro de bit satisfatória. Os resultados obtidos mostram uma correspondência bastante próxima dos valores teóricos, onde a arquitetura com sobre-amostragem 2x apresenta uma tolerância de jitter de, aproximadamente, 12UI e a arquitetura com sobre-amostragem 3x apresenta uma tolerância de, aproximadamente, 23UI para baixas frequências de jitter

High-Speed Low-Voltage Line Driver for SerDes Applications

The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable