New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Components for Wide Bandwidth Signal Processing in Radio Astronomy

In radio astronomy wider observing bandwidths are constantly desired for the reasons of improved sensitivity and velocity coverage. As observing frequencies move steadily higher these needs become even more pressing. In order to process wider bandwidths, components that can perform at higher frequencies are required. The chief limiting component in the area of digital spectrometers and correlators is the digitiser. This is the component that samples and quantises the bandwidth of interest for further digital processing, and must function at a sample rate of at least twice the operating bandwidth. In this work a range of high speed digitiser integrated circuits (IC) are designed using an advanced InP HBT semiconductor process and their performance limits analysed. These digitiser ICs are shown to operate at up to 10 giga-samples/s, significantly faster than existing digitisers, and a complete digitiser system incorporating one of these is designed and tested that operates at up to 4 giga-samples/s, giving 2 GHz bandwidth coverage. The digitisers presented include a novel photonic I/O digitiser which contains an integrated photonic interface and is the first digitiser device reported with integrated photonic connectivity. In the complementary area of analogue correlators the limiting component is the device which performs the multiplication operation inherent in the correlation process. A 15 GHz analogue multiplier suitable for such systems is designed and tested and a full noise analysis of multipliers in analogue correlators presented. A further multiplier design in SiGe HBT technology is also presented which offers benefits in the area of low frequency noise. In the effort to process even wider bandwidths, applications of photonics to digitisers and multipliers are investigated. A new architecture for a wide bandwidth photonic multiplier is presented and its noise properties analysed, and the use of photonics to increase the sample rate of digitisers examined

CMOS dual-modulus prescaler design for RF frequency synthesizer applications.

Ng Chong Chon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 100-103).Abstract in English and Chinese.摘要 --- p.iiiAcknowledgments --- p.ivContents --- p.viList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Thesis Organization --- p.4Chapter Chapter 2 --- DMP Architecture --- p.6Chapter 2.1 --- Conventional DMP --- p.6Chapter 2.1.1 --- Operating Principle --- p.7Chapter 2.1.2 --- Disadvantages --- p.10Chapter 2.2 --- Pre-processing Clock Architecture --- p.10Chapter 2.2.1 --- Operating Principle --- p.11Chapter 2.2.2 --- Advantages and Disadvantages --- p.12Chapter 2.3 --- Phase-switching Architecture --- p.13Chapter 2.3.1 --- Operating Principle --- p.13Chapter 2.3.2 --- Advantages and Disadvantages --- p.14Chapter 2.4 --- Summary --- p.15Chapter Chapter 3 --- Full-Speed Divider Design --- p.16Chapter 3.1 --- Introduction --- p.16Chapter 3.2 --- Working Principle --- p.16Chapter 3.3 --- Design Issues --- p.18Chapter 3.4 --- Device Sizing --- p.19Chapter 3.5 --- Layout Considerations --- p.20Chapter 3.6 --- Input Sensitivity --- p.22Chapter 3.7 --- Modeling --- p.24Chapter 3.8 --- Review on Different Divider Designs --- p.28Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34Chapter 3.9 --- Summary --- p.42Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43Chapter 4.1 --- Introduction --- p.43Chapter 4.2 --- Proposed DMP Topology --- p.46Chapter 4.3 --- Circuit Design and Implementation --- p.49Chapter 4.4 --- Simulation Results --- p.51Chapter 4.5 --- Summary --- p.53Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Proposed DMP Topology --- p.56Chapter 5.3 --- Circuit Design and Implementation --- p.59Chapter 5.3.1 --- Divide-by-4 stage --- p.59Chapter 5.3.2 --- TSPC dividers --- p.63Chapter 5.3.3 --- Phase-selection Network --- p.63Chapter 5.3.4 --- Mode-control Logic --- p.64Chapter 5.3.5 --- Duty-cycle Transformer --- p.65Chapter 5.3.6 --- Glitch Problem --- p.66Chapter 5.3.7 --- Phase-mismatch Problem --- p.70Chapter 5.4 --- Simulation Results --- p.70Chapter 5.5 --- Summary --- p.74Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75Chapter 6.1 --- Introduction --- p.75Chapter 6.2 --- Proposed DMP Architecture --- p.75Chapter 6.3 --- Divide-by-4 Stage --- p.76Chapter 6.3.1 --- Current-switch Combining --- p.76Chapter 6.3.2 --- Capacitive Load Reduction --- p.77Chapter 6.4 --- Simulation Results --- p.81Chapter 6.5 --- Summary --- p.83Chapter Chapter 7 --- Experimental Results --- p.84Chapter 7.1 --- Introduction --- p.84Chapter 7.2 --- Equipment Setup --- p.84Chapter 7.3 --- Measurement Results --- p.85Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93Chapter 7.3 --- Summary --- p.96Chapter Chapter 8 --- Conclusions and Future Works --- p.98Chapter 8.1 --- Conclusions --- p.98Chapter 8.2 --- Future Works --- p.99References --- p.100Publications --- p.10

Low phase noise 2 GHz Fractional-N CMOS synthesizer IC

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2.Dissertation (MEng)--University of Pretoria, 2010.Electrical, Electronic and Computer Engineeringunrestricte

Studies of methods of pre-launch testing of satellite radar altimeters

The radar altimeter operating in a pulse-limited mode has been successful in charting the ocean surfaces of the Earth. The scientific community, in a drive to map rougher terrain, have adopted the same principle. However in order to overcome the problem of slope- induced error, the range window may be widened or narrowed in accordance with the surface roughness. The ERS-1 altimeter included a second range window for operation over ice, but which had to be controlled by macro-command from the ground. The Advanced Terrain-Tracking Altimeter is a prototype altimeter which has an on-board resolution-switching algorithm, allowing the range window to be changed appropriately. This thesis focuses on methods of pre-launch testing of advanced radar altimeters. The early chapters review some of the calibration and testing methods used for the ERS-1 altimeter, presenting a critical assessment of some of the pre-launch methods. The testing procedure for the Adaptive Terrain-Tracking Altimeter is significantly more complex because of the extra resolution-switching algorithm, and a return signal simulator is identified as an essential element in testing the adaptive resolution prior to launch. The core of the thesis therefore describes a novel method of return signal simulation in which sequences of realistic echoes, from all types of surface, are fed in real time to the prototype altimeter, at the appropriate resolution, with the appropriate fading characteristics, and at the appropriate instant in time. Such a simulator is feasible only if the simulated echo is modelled in the deramp domain (i.e range window space) rather than actual delay time. Then the Fourier Transforms of the echoes, rather than the echoes themselves, are calculated at the full pulse repetition frequency and are stored in a memory. The resolution may then be varied by altering the rate at which the echoes are read out of memory. A prototype Return Signal Simulator is built, tested and shown to be capable of testing the Adaptive Terrain-Tracking Altimeter. A test philosophy is defined to assist the testing of the prototype altimeter, which will be undertaken by British Aerospace. A preliminary analysis, using a software implementation of the return signal simulator and realistic echoes, demonstrated that the Model Free Tracker has a superior tracking performance than the generally preferred Offset Centre Of Gravity tracking algorithm. However both algorithms suffer from problems, and these problems are identified. Finally a new approach to the analysis of the effect of chirp phase errors is presented, which leads to a quantitative expression for the height error resulting from chirp phase distortion. Such an approach can be used to apply a correction to the height estimate, unlike previous approaches which could only be used to set a specification for altimeter design

Design, Fabrication and Veri cation of a Mixed-Signal XY Zone Monitoring Circuit and its Application to a Phase Lock Loop Circuit

El presente proyecto de final de carrera se centra en el diseño, análisis e implementación en silicio de una metodología de test/diagnosis basada en la comparación de firmas digitales generadas a partir de curvas de Lissajous. Se muestra su aplicación para testar la etapa de filtro de un circuito de bucle de enganche de fase (phase lock loop, PLL), así como los resultados experimentales de su implementación en tecnología CMOS de 65 nm. La obtención de las firmas digitales se consigue mediante el uso de un circuito monitor, el cual, a partir de la composición de dos señales periódicas del circuito a analizar, genera, para cada punto de la curva de Lissajous, un valor digital. La utilización de varios monitores con gurados de la manera adecuada permite una completa teselación del plano en diferentes zonas y por tanto, la generación de distintos códigos digitales (firma) a medida que la curva de Lissajous evoluciona en el tiempo. El test del circuito y/o diagnosis del posible defecto se realiza mediante la comparación de la signatura golden o sin defecto y la signatura generada por el circuito testado. Para la comparación de firmas se emplea el concepto de distancia de Hamming entre códigos a modo de métrica de discrepancia. A partir de los valores precalculados de la métrica para cada posible valor del defecto se consigue realizar la diagnosis de este para el parámetro en estudio. El trabajo se enmarca en el diseño de circuitos integrados de muy alta escala de integración usando una tecnología CMOS de actualidad (65 nm). Es por ello que se requieren técnicas de diseño analógico específicas, como lo son las estrategias centroidales para la elaboración de layouts o el correcto modelado de transistores nanométricos. Para esto último se hace uso del modelo Berkeley, el cual, debidamente ajustado a la tecnología empleada, proporciona aproximaciones muy aceptables y con relativa facilidad de uso. Con el objetivo de verificar la metodología de test/diagnosis propuesta, se hace uso de una aplicación Matlab que permite simular el comportamiento del circuito a testar en diferentes situaciones. Es posible excitar el circuito con distintas entradas, cambiar los parámetros de este, introducir defectos, o emplear distintos conjuntos de curvas para teselar el plano. La aplicación resulta fundamental para efectuar el proceso de diagnosis pues relaciona la cantidad de defecto con los valores de discrepancia obtenidos con la métrica definida. Finalmente, se presentan los resultados experimentales obtenidos con el chip fabricado. Se constata el correcto comportamiento de este y la validez de la metodología de test/diagnosis propuesta

Dielectric relaxation time spectroscopy for tissue characterisation

This thesis is concerned with Electrical Impedance Spectroscopy (EIS), a noninvasive technique for characterising biological tissue and distinguishing pathology. The thesis is focused on the development of an improved method for extracting physiologically related parameters from the measured impedance data in vivo and instrumentation for spectroscopic measurements. In EIS, the electrical properties of physiological tissues, defined by their composition and structure, are measured as functions of frequency. Experimental observations of the existence of dielectric dispersions caused by distributions of dielectric relaxation time (DRT) constants were made on different types of biological material. It is postulated that widely used approaches for modelling these electrical properties are fundamentally flawed. The research work concentrates on the reconstruction of DRT spectra directly from the measured frequency response. The reconstruction problem involves inversion of a linear operator and like many inverse problems, is complicated by the ill-posed nature of the problem. In this thesis an inversion algorithm - Galerkin Regularised Inverse Method (GRIM) - based on standard mathematical methods is developed. The DRT spectrum establishes a link between the raw impedance data and the physiological structure and function of biological tissues. The GRIM yields a large number of independent parameters each related to process on a different scale. Special care was taken in testing the method on simulated data and improving its resolution. The thesis is also concerned with the design and practical implementation of EIS systems. Two approaches are considered: systems based on commercially available Impedance Analysers and systems designed specially for studies in vivo. To evaluate the GRIM, an Impedance Analyser, benefitting from a higher accuracy and a wider frequency range, is used. To meet the more rigorous specification demanded for studies on living human tissues, an electrical impedance spectrometer is developed. The suitability of different current sources is investigated. This research work includes studies of animal tissue in vitro and in vivo. Optimal experiments are defined in terms of the measurement frequency range and the entire experimental protocol for dielectric spectroscopy is established. These biological data are used to evaluate the GRIM. A comparison between different tissue classes in vivo is made. From studying ischemic tissues, it is postulated and verified that physiological differences and changes can be measured using the technique of DRT spectroscopy

Analysis, simulation and design of nonlinear RF circuits

The PhD project consists of two parts. The first part concerns the development of Computer Aided Design (CAD) algorithms for high-frequency circuits. Novel Padébased algorithms for numerical integration of ODEs as arise in high-frequency circuits are proposed. Both single- and multi-step methods are introduced. A large part of this section of the research is concerned with the application of Filon-type integration techniques to circuits subject to modulated signals. Such methods are tested with analog and digital modulated signals and are seen to be very effective. The results confirm that these methods are more accurate than the traditional trapezoidal rule and Runge-Kutta methods. The second part of the research is concerned with the analysis, simulation and design of RF circuits with emphasis on injection-locked frequency dividers (ILFD) and digital delta-sigma modulators (DDSM). Both of these circuits are employed in fractional-N frequency synthesizers. Several simulation methods are proposed to capture the locking range of an ILFD, such as the Warped Multi-time Partial Differential Equation (WaMPDE) and the Multiple-Phase-Condition Envelope Following (MPCENV) methods. The MPCENV method is the more efficient and accurate simulation technique and it is recommended to obviate the need for expensive experiments. The Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM) is simulated in MATLAB and analysed mathematically. A novel structure employing multimoduli, termed the MM-MASH, is proposed. The goal in this design work is to reduce the noise level in the useful frequency band of the modulator. The success of the novel structure in achieving this aim is confirmed with simulations