A novel 3D NoC scheme for high throughput unicast and multicast routing protocols

Nova 3D-NoC arhitektura dizajnirana je s većom mogućnošću prihvaćanja komprimiranih podataka. Predložena shema daje značajne rezultate u odnosu na učinkovitost i propusnu moć mreže. U toj shemi, predloženoj za 3D-NoC, podaci koje je potrebno prenijeti, komprimirani su već prije prijenosa tako da je veličina paketa s podacima smanjena već prije prenošenja. Pri prijemu, originalni podaci se obnavljaju dekompresijom kodiranih podataka. Golomb-Rice algoritam se primjenjuje za razvoj i primjenu kodera i dekodera hardvera (kodek dekoder). Dobiven je rezultat i za unicast i multicast usmjeravanje. Povećanje učinkovitosti i propusne moći za predloženi 3D-NoC (unicast) je 9,25 % odnosno 17,61 %. Slično tome, poboljšanje učinkovitosti i propusne moći za predloženi 3D-NoC (multicast) je 8,65 % odnosno 14,66 %. Nadalje, rezultati pokazuju da je poboljšanje veće kod manjih širina pojasa, a to znači da predloženi 3D-NoC dobro funkcionira u slučaju uskih širina pojasa.Novel 3D-NoC architecture has been designed by expanding the impression of lossless compression of data. The proposed design shows remarkable results in terms of power efficiency and network throughput. In this scheme, proposed for 3D-NoC, the data to be transmitted is compressed on the transmitting side, so that the data packet is reduced before transmitting. And at the receiver, the original data is restored by decompressing the encoded data. Golomb-Rice algorithm is utilized to develop and implement the hardware encoder and decoder (Codec). The result is evaluated for both unicast and multicast routing. The improvement in power efficiency and throughput for proposed 3D-NoC (unicast) is 9,25 % and 17,61 % respectively. In similar, the improvement in power efficiency and throughput for proposed 3D-NoC (multicast) is 8,65 % and 14,66 % respectively. Further, from the result we observed that the improvement variation is higher for smaller bandwidth, which means the proposed 3D-NoC works well in case of narrow bandwidth

Indirect contact probing method for characterizing vertical interconnects

Department of Electrical EngineeringRecently, vertical interconnects in wafer-level are used to achieve system integration with stacked chips. Although the wafer-level vertical interconnects provide smaller interconnection delay and lower power consumption, popularizing the technology is difficult due to testing issues. A main difficulty in testing vertical interconnects comes from that possible damages caused by the direct-contact probing. Therefore, an indirect contact probing method is presented for safe characterization in waver level. The proposed method is based on the capacitive coupling method. Utilizing a dielectric contactor, the sensitivity of capacitive coupling can be improved with ensuring the protection of vertical interconnects. In addition, extra probe control module and sensor electronics are not required since the dielectric contactor maintains the constant gap. The proposed method is verified in both cases of a single-pair via and multiple vias. The procedure of the proposed method for a single-pair vias starts with one-port calibration. To apply one-port calibration, we have measurements on three different calibration vias by the indirect and the direct-contact probing. From the measurement data, the characteristic of dielectric contactor is fully characterized. After the dielectric contactor is mounted on the DUT containing vertical interconnects, the DUT is measured by the indirect-contact probing manner. Finally, de-embedding the dielectric contactor portion, we can obtain the characteristic of a single-pair via. The proposed method is verified in printed circuit board (PCB) level. The extracted via impedances show a good agreement with the direct-contact probing in frequency ranges 0.8 GHz to 30 GHz and 2.5 GHz to 18 GHz by simulations and measurements, respectively. In the case of multi-via testing, the procedure is similar to a single-pair via extraction but additional fixtures are required. By adopting the socket and calibration substrates, the dielectric contactor consisting of multiple pads can be characterized. From dielectric contactor characteristics corresponding to each via, multiple vias can be extracted based on the reference plane. The extracted impedances of multiple vias show a good agreement with the direct-contact probing up to 24 GHz by simulations and 22 GHz by measurements. From the extracted impedances, we can diagnose all defects among multiple vias. Since the proposed method for multi-via test is limited to testing, the indirect contact probing method for the multi-port characterization is also proposed. It characterizes a multi-port network of a DUT by de-embedding the multi-port characteristics of the dielectric contactor, hence we can also capture inter-via couplings from a multi-port network. Based on simulations, a two-port network is successfully characterized in the range of 0.8 GHz to 24 GHz.ope

HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY

Hardware security is a serious emerging concern in chip designs and applications. Due to the globalization of the semiconductor design and fabrication process, integrated circuits (ICs, a.k.a. chips) are becoming increasingly vulnerable to passive and active hardware attacks. Passive attacks on chips result in secret information leaking while active attacks cause IC malfunction and catastrophic system failures. This thesis focuses on detection and prevention methods against active attacks, in particular, hardware Trojan (HT). Existing HT detection methods have limited capability to detect small-scale HTs and are further challenged by the increased process variation. We propose to use differential Cascade Voltage Switch Logic (DCVSL) method to detect small HTs and achieve a success rate of 66% to 98%. This work also presents different fault tolerant methods to handle the active attacks on symmetric-key cipher SIMON, which is a recent lightweight cipher. Simulation results show that our Even Parity Code SIMON consumes less area and power than double modular redundancy SIMON and Reversed-SIMON, but yields a higher fault -detection-failure rate as the number of concurrent faults increases. In addition, the emerging technology, memristor, is explored to protect SIMON from passive attacks. Simulation results indicate that the memristor-based SIMON has a unique power characteristic that adds new challenges on secrete key extraction

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Exploring Adaptive Implementation of On-Chip Networks

As technology geometries have shrunk to the deep submicron regime, the communication delay and power consumption of global interconnections in high performance Multi- Processor Systems-on-Chip (MPSoCs) are becoming a major bottleneck. The Network-on- Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects and integration of large number of Processing Elements (PEs) on a chip. The choice of routing protocol and NoC structure can have a significant impact on performance and power consumption in on-chip networks. In addition, building a high performance, area and energy efficient on-chip network for multicore architectures requires a novel on-chip router allowing a larger network to be integrated on a single die with reduced power consumption. On top of that, network interfaces are employed to decouple computation resources from communication resources, to provide the synchronization between them, and to achieve backward compatibility with existing IP cores. Three adaptive routing algorithms are presented as a part of this thesis. The first presented routing protocol is a congestion-aware adaptive routing algorithm for 2D mesh NoCs which does not support multicast (one-to-many) traffic while the other two protocols are adaptive routing models supporting both unicast (one-to-one) and multicast traffic. A streamlined on-chip router architecture is also presented for avoiding congested areas in 2D mesh NoCs via employing efficient input and output selection. The output selection utilizes an adaptive routing algorithm based on the congestion condition of neighboring routers while the input selection allows packets to be serviced from each input port according to its congestion level. Moreover, in order to increase memory parallelism and bring compatibility with existing IP cores in network-based multiprocessor architectures, adaptive network interface architectures are presented to use multiple SDRAMs which can be accessed simultaneously. In addition, a smart memory controller is integrated in the adaptive network interface to improve the memory utilization and reduce both memory and network latencies. Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package density as compared to traditional 2D ICs. In addition, combining the benefits of 3D IC and NoC schemes provides a significant performance gain for 3D architectures. In recent years, inter-layer communication across multiple stacked layers (vertical channel) has attracted a lot of interest. In this thesis, a novel adaptive pipeline bus structure is proposed for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration. In addition, two mesh-based topologies for 3D architectures are also introduced to mitigate the inter-layer footprint and power dissipation on each layer with a small performance penalty.Siirretty Doriast

Reliability Analysis of Electrotechnical Devices

This is a book on the practical approaches of reliability to electrotechnical devices and systems. It includes the electromagnetic effect, radiation effect, environmental effect, and the impact of the manufacturing process on electronic materials, devices, and boards

Embedded dynamic programming networks for networks-on-chip

PhD ThesisRelentless technology downscaling and recent technological advancements in three dimensional integrated circuit (3D-IC) provide a promising prospect to realize heterogeneous system-on-chip (SoC) and homogeneous chip multiprocessor (CMP) based on the networks-onchip (NoCs) paradigm with augmented scalability, modularity and performance. In many cases in such systems, scheduling and managing communication resources are the major design and implementation challenges instead of the computing resources. Past research efforts were mainly focused on complex design-time or simple heuristic run-time approaches to deal with the on-chip network resource management with only local or partial information about the network. This could yield poor communication resource utilizations and amortize the benefits of the emerging technologies and design methods. Thus, the provision for efficient run-time resource management in large-scale on-chip systems becomes critical. This thesis proposes a design methodology for a novel run-time resource management infrastructure that can be realized efficiently using a distributed architecture, which closely couples with the distributed NoC infrastructure. The proposed infrastructure exploits the global information and status of the network to optimize and manage the on-chip communication resources at run-time. There are four major contributions in this thesis. First, it presents a novel deadlock detection method that utilizes run-time transitive closure (TC) computation to discover the existence of deadlock-equivalence sets, which imply loops of requests in NoCs. This detection scheme, TC-network, guarantees the discovery of all true-deadlocks without false alarms in contrast to state-of-the-art approximation and heuristic approaches. Second, it investigates the advantages of implementing future on-chip systems using three dimensional (3D) integration and presents the design, fabrication and testing results of a TC-network implemented in a fully stacked three-layer 3D architecture using a through-silicon via (TSV) complementary metal-oxide semiconductor (CMOS) technology. Testing results demonstrate the effectiveness of such a TC-network for deadlock detection with minimal computational delay in a large-scale network. Third, it introduces an adaptive strategy to effectively diffuse heat throughout the three dimensional network-on-chip (3D-NoC) geometry. This strategy employs a dynamic programming technique to select and optimize the direction of data manoeuvre in NoC. It leads to a tool, which is based on the accurate HotSpot thermal model and SystemC cycle accurate model, to simulate the thermal system and evaluate the proposed approach. Fourth, it presents a new dynamic programming-based run-time thermal management (DPRTM) system, including reactive and proactive schemes, to effectively diffuse heat throughout NoC-based CMPs by routing packets through the coolest paths, when the temperature does not exceed chip’s thermal limit. When the thermal limit is exceeded, throttling is employed to mitigate heat in the chip and DPRTM changes its course to avoid throttled paths and to minimize the impact of throttling on chip performance. This thesis enables a new avenue to explore a novel run-time resource management infrastructure for NoCs, in which new methodologies and concepts are proposed to enhance the on-chip networks for future large-scale 3D integration.Iraqi Ministry of Higher Education and Scientific Research (MOHESR)