Unambiguous Acquisition and Tracking Technique for General BOC Signals

This article presents a new unambiguous acquisition and tracking technique for general Binary Offset Carrier (BOC) ranging signals, which will be used in modern GPS, European Galileo system and Chinese BeiDou system. The test criterion employed in this technique is based on a synthesized correlation function which completely removes positive side peaks while keeping the sharp main peak. Simulation results indicate that the proposed technique completely removes the ambiguity threat in the acquisition process while maintaining relatively higher acquisition performance for low order BOC signals. The potential false lock points in the tracking phase for any order BOC signals are avoided by using the proposed method. Impacts of thermal noise and multipath on the proposed technique are investigated; the simulation results show that the new method allows the removal of false lock points with slightly degraded tracking performance. In addition, this method is convenient to implement via logic circuits

A one femtojoule athermal silicon modulator

Silicon photonics has emerged as the leading candidate for implementing ultralow power wavelength division multiplexed communication networks in high-performance computers, yet current components (lasers, modulators, filters, and detectors) consume too much power for the femtojouleclass links that will ultimately be required. Here, we propose, demonstrate, and characterize the first modulator to achieve simultaneous high-speed (25-Gb/s), low voltage (0.5VPP) and efficient 1-fJ/bit error-free operation while maintaining athermal operation. Both the low energy and athermal operation were enabled by a record free-carrier accumulation/depletion response obtained in a vertical p-n junction device that at 250-pm/V (30-GHz/V) is up to ten times larger than prior demonstrations. Over a 7.5{\deg}C temperature range, the massive electro-optic response was used to compensate for thermal drift without increasing energy consumption and over a 10{\deg}C temperature range, increasing energy consumption by only 2-fJ/bit. The results represent a new paradigm in modulator development, one where thermal compensation is achieved electro-optically.Comment: 23 pages, 5 figure

What's Blocking the Sun?: Solar Photovoltaics for the U.S. Commercial Market

Provides an overview of installation trends and investment climate for solar photovoltaics in the U.S. commercial sector, including policy and economic obstacles. Recommends strategies for the solar industry, the commercial sector, and policy makers

An Overview of Fully Integrated Switching Power Converters Based on Switched-Capacitor versus Inductive Approach and Their Advanced Control Aspects

This paper reviews and discusses the state of the art of integrated switched-capacitor and integrated inductive power converters and provides a perspective on progress towards the realization of efficient and fully integrated DC–DC power conversion. A comparative assessment has been presented to review the salient features in the utilization of transistor technology between the switched-capacitor and switched inductor converter-based approaches. First, applications that drive the need for integrated switching power converters are introduced, and further implementation issues to be addressed also are discussed. Second, different control and modulation strategies applied to integrated switched-capacitor (voltage conversion ratio control, duty cycle control, switching frequency modulation, Ron modulation, and series low drop out) and inductive converters (pulse width modulation and pulse frequency modulation) are then discussed. Finally, a complete set of integrated power converters are related in terms of their conditions and operation metrics, thereby allowing a categorization to provide the suitability of converter technologies

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System on a Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitance nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence

Developing Prognostic Models Using Duality Principles for DC-to-DC Converters

Within the field of Integrated System Health Management, there is still a lack of technological approaches suitable for the creation of adequate prognostic model for large applications whereby a number of similar or even identical subsystems and components are used. Existing similarity among a number of different systems, which are comprised of similar components but with different topologies, can be employed to assign the prognostics of one system to other systems using an inference engine. In the process of developing prognostics, this approach will thereby save resources and time. This paper presents a radically novel approach for building prognostic models based on system similarity in cases where duality principle in electrical systems is utilized. In this regard, unified damage model is created based on standard Tee/Pi models, prognostics model based on transfer functions, and remaining useful life (RUL) estimator based on how energy relaxation time of system is changed due to degradation. An advantage is that the prognostic model can be generalized such that a new system could be developed on the basis and principles of the prognostic model of other systems. Simple electronic circuits, dc-to-dc converters, are to be used as an experiment to exemplify the potential success of the proposed technique validated with prognostics models from particle filter

Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure

Both random and systematic within-die process variations (PV) are growing more severe with shrinking geometries and increasing die size. Escalation in the variations in delay and power with reductions in feature size places higher demands on the accuracy of variation models. Their availability can be used to improve yield, and the corresponding profitability and product quality of the fabricated integrated circuits (ICs). Sources of within-die variations include optical source limitations, and layout-based systematic effects (pitch, line-width variability, and microscopic etch loading). Unfortunately, accurate models of within-die PVs are becoming more difficult to derive because of their increasingly sensitivity to design-context. Embedded test structures (ETS) continue to play an important role in the development of models of PVs and as a mechanism to improve correlations between hardware and models. Variations in path delays are increasing with scaling, and are increasingly affected by neighborhood\u27 interactions. In order to fully characterize within-die variations, delays must be measured in the context of actual core-logic macros. Doing so requires the use of an embedded test structure, as opposed to traditional scribe line test structures such as ring oscillators (RO). Accurate measurements of within-die variations can be used, e.g., to better tune models to actual hardware (model-to-hardware correlations). In this research project, I propose an embedded test structure called REBEL (Regional dELay BEhavior) that is designed to measure path delays in a minimally invasive fashion; and its architecture measures the path delays more accurately. Design for manufacture-ability (DFM) analysis is done on the on 90 nm ASIC chips and 28nm Zynq 7000 series FPGA boards. I present ASIC results on within-die path delay variations in a floating-point unit (FPU) fabricated in IBM\u27s 90 nm technology, with 5 pipeline stages, used as a test vehicle in chip experiments carried out at nine different temperature/voltage (TV) corners. Also experimental data has been analyzed for path delay variations in short vs long paths. FPGA results on within-die variation and die-to-die variations on Advanced Encryption System (AES) using single pipelined stage are also presented. Other analysis that have been performed on the calibrated path delays are Flip Flop propagation delays for both rising and falling edge (tpHL and tpLH), uncertainty analysis, path distribution analysis, short versus long path variations and mid-length path within-die variation. I also analyze the impact on delay when the chips are subjected to industrial-level temperature and voltage variations. From the experimental results, it has been established that the proposed REBEL provides capabilities similar to an off-chip logic analyzer, i.e., it is able to capture the temporal behavior of the signal over time, including any static and dynamic hazards that may occur on the tested path. The ASIC results further show that path delays are correlated to the launch-capture (LC) interval used to time them. Therefore, calibration as proposed in this work must be carried out in order to obtain an accurate analysis of within-die variations. Results on ASIC chips show that short paths can vary up to 35% on average, while long paths vary up to 20% at nominal temperature and voltage. A similar trend occurs for within-die variations of mid-length paths where magnitudes reduced to 20% and 5%, respectively. The magnitude of delay variations in both these analyses increase as temperature and voltage are changed to increase performance. The high level of within-die delay variations are undesirable from a design perspective, but they represent a rich source of entropy for applications that make use of \u27secrets\u27 such as authentication, hardware metering and encryption. Physical unclonable functions (PUFs) are a class of primitives that leverage within-die-variations as a means of generating random bit strings for these types of applications, including hardware security and trust. Zynq FPGAs Die-to-Die and within-die variation study shows that on average there is 5% of within-Die variation and the range of die-to-Die variation can go upto 3ns. The die-to-Die variations can be explored in much further detail to study the variations spatial dependance. Additionally, I also carried out research in the area data mining to cater for big data by focusing the work on decision tree classification (DTC) to speed-up the classification step in hardware implementation. For this purpose, I devised a pipelined architecture for the implementation of axis parallel binary decision tree classification for meeting up with the requirements of execution time and minimal resource usage in terms of area. The motivation for this work is that analyzing larger data-sets have created abundant opportunities for algorithmic and architectural developments, and data-mining innovations, thus creating a great demand for faster execution of these algorithms, leading towards improving execution time and resource utilization. Decision trees (DT) have since been implemented in software programs. Though, the software implementation of DTC is highly accurate, the execution times and the resource utilization still require improvement to meet the computational demands in the ever growing industry. On the other hand, hardware implementation of DT has not been thoroughly investigated or reported in detail. Therefore, I propose a hardware acceleration of pipelined architecture that incorporates the parallel approach in acquiring the data by having parallel engines working on different partitions of data independently. Also, each engine is processing the data in a pipelined fashion to utilize the resources more efficiently and reduce the time for processing all the data records/tuples. Experimental results show that our proposed hardware acceleration of classification algorithms has increased throughput, by reducing the number of clock cycles required to process the data and generate the results, and it requires minimal resources hence it is area efficient. This architecture also enables algorithms to scale with increasingly large and complex data sets. We developed the DTC algorithm in detail and explored techniques for adapting it to a hardware implementation successfully. This system is 3.5 times faster than the existing hardware implementation of classification.\u2

Authentication of GNSS signal by Information-theoretic security

In this work a new authentication protocol for global navigation satellite system (GNSS) signals is proposed. The protocol uses artificial noise to confuse the adversary and send an initially hidden verification message. Correctness is based on information-theoretic security and performances are evaluated in terms of secrecy capacityope