Compact Realizations of Embedded Filters in Organic Substrates

Making communication devices smaller, lighter, and cheaper has been the driving force behind the development of new technologies which have made the cellular phones and wireless networks we now take for granted possible. The frequent emphasis on miniaturization particularly has required the development of a variety of new approaches to creating communications circuits. One such technology that has attracted a great deal of attention in recent years is passives that are embedded into the package of communications integrated circuits. Using these devices reduces the amount of surface area required to implement a communications device, in addition to potentially improving performance and making them cost less. One area of application which is immediately obvious is the RF filtering which is required in communication devices. The primary contribution of the present work is to establish a procedure for using such embedded passives to implement RF filters. While a large body of work has been previously devoted to the modeling and creation of individual embedded passives, the challenge of combining them into functional networks for use in communications system has not yet been the subject of a significant amount of academic analysis. By consolidating the knowledge gained by previous work concerning the modeling and optimization of embedded passives, the present work attempts to formulate an optimized procedure for creating embedded passive filter networks. The present work presents the design and implementation of LC ladder filters for microwave frequencies using passives embedded in an organic substrate provided by Intel Corporation. The work presents an efficient and accurate methodology for the design and implementation of such filters in a limited footprint area, with an emphasis on creating a straightforward, fast design procedure. For both embedded passive inductors and capacitors a parameterized three dimensional model suitable for use in a fullwave solver has been developed. An exhaustive documentation of the simulation parameters used to simulate these structures is provided in order to assist others in repeating the work presented here. In order to create embedded filters, libraries spanning the design space of both embedded inductors and capacitors have been formed. Inductors with different numbers of turns, trace widths, trace spacing, and inner diameters have been simulated from 1 to 10 GHz and analyzed to obtain the inductance, self resonant frequency, Q, and parasitic effects. Capacitors with plate areas ranging from a minimum size up to 1 mm are also simulated and empirical formulas for their capacitance, resistance and inductance are provided. Based on this, a design methodology is proposed and documented. The design methodology includes compensation for the coupling effects that exist between embedded passives placed in close proximity to one another. Based on the simulated coupling effects suggestions for layout are made. A design procedure developed in this work has been applied to a three pole and five pole low pass filters. The filters\u27 characteristics show an excellent agreement the response of the LC ladder filter. Finally the work presents a study of some the effects of manufacturing tolerances on filter construction. Based on the preliminary findings of the investigation the most detrimental effects are determined and further work to explore these issues is suggested

Current and Future Research Trends in Substrate Integrated Waveguide Technology

Substrate Integrated Waveguide (SIW) technology is the most promising candidate for the implementation of millimeter-wave (mm-wave) integrated circuits and systems for the next decade. Based on planar dielectric substrates with top and bottom metal layers perforated with metalized holes, SIW structures offer a compact, low loss, flexible, and cost-effective solution for integrating active circuits, passive components and radiating elements on the same substrate. This paper presents an overview of the current status and future trends of academic and industrial research on SIW technology. The historical development of SIW components and circuits is briefly outlined, and the current research topics are discussed: they include the development of numerical techniques for the modeling and design of SIW components, the investigation of novel compact and broadband interconnects, the determination of design solutions for loss minimization. Future research trends are also discussed: they mainly aim at the implementation of SIW components at higher frequency (60-350 GHz) and the integration of complete Systems-on-Substrate (SoS)

Entire domain basis function expansion of the differential surface admittance for efficient broadband characterization of lossy interconnects

This article presents a full-wave method to characterize lossy conductors in an interconnect setting. To this end, a novel and accurate differential surface admittance operator for cuboids based on entire domain basis functions is formulated. By combining this new operator with the augmented electric field integral equation, a comprehensive broadband characterization is obtained. Compared with the state of the art in differential surface admittance operator modeling, we prove the accuracy and improved speed of the novel formulation. Additional examples support these conclusions by comparing the results with commerical software tools and with measurements

Modeling Noise Coupling Between Package and PCB Power/Ground Planes with an Efficient 2-D FDTD/Lumped Element Method

An efficient numerical approach based on the 2-D finite-difference time-domain (FDTD) method is proposed to model the power/ground plane noise or simultaneously switching noise (SSN), including the interconnect effect between the package and the print circuit board (PCB). The space between the power and ground planes on the package and PCB are meshed with 2-D cells. The equivalent R-L-C circuits of the via and the solder balls connecting the package and PCB can be incorporated into a 2-D Yee cell based on a novel integral formulation in the time domain. An efficient recursive updating algorithm is proposed to fit the lumped networks into the Yee equations. A test sample of a ball grid array (BGA) package mounted on a PCB was fabricated. The power/ground noise coupling behavior was measured and compared with the simulation. The proposed method significantly reduces the computing time compared with other full-wave numerical approaches

INVESTIGATION OF TECHNIQUES FOR REDUCING UNINTENTIONAL ELECTROMAGNETIC EMISSIONS FROM ELECTRONIC CIRCUITS AND SYSTEMS

This dissertation describes three independent studies related to techniques for reducing unintentional electromagnetic emissions from electronic circuits and systems. The topics covered are: low-inductance multi-layer ceramic capacitor for high frequency circuit board decoupling, the application of imbalance difference model to various circuit board and cable geometries, and balanced cable interface for reducing common-mode currents from power inverter. The first chapter discusses the importance and the meaning of the connection inductance associated with MLCCs and analyzes the effect of plate orientation in MLCCs. It demonstrates that vertically oriented plates have no more or less inductance than horizontally oriented plates when the overall dimensions of the plate stack are similar. Decoupling capacitance options at the various levels of a high-speed circuit is investigated to determine the range of frequencies that decoupling at each level is likely to be is effective. Innovative low-inductance capacitive-stem capacitor configurations are described and their connection impedance is compared to that of standard surface-mounted capacitors. The second chapter investigates the imbalance difference model that is a method for modeling how differential-mode signal currents are converted to common-mode noise currents. Various cable geometries to determine how well imbalance factor`s values of DM-to-CM conversion compare to full-wave calculations are explored. The imbalance difference model can be applied to cables with more than two conductors are demonstrated. The third chapter investigates the balanced cable interface for reducing common-mode currents from power inverter. The concept of a balancing network to reduce the common-mode currents on power inverter cables above 30 MHz is introduced. An experimental test set-up is used to demonstrate the effect of a balancing network on the common-mode current, differential-mode current and the common-mode rejection ratio on a balanced cable with an imbalanced termination. The balancing network is also evaluated using a 3-phase brushless DC motor driver to verify its effectiveness in a real application

Design of a high quality factor spiral inductors in RF MCM-D

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 79-82).This thesis studies the design and fabrication of spiral inductors for use in Radio Frequency (RF) applications. A design methodology is developed to search an inductor design space efficiently using existing simulation software. The methodology allows designers to specify a desired inductance, total area, and frequency of operation instead of the geometrical parameters required by most design software. An implementation of the methodology that finds devices with optimal quality factor at a given frequency is presented. Several inductor designs are generated using this implementation, and the devices are fabricated in the Draper Laboratory, Inc. Multichip Module-Deposited (MCM-D) process. Simulated characteristics of the devices are verified using experimental measurements, and deviations from predicted performance are discussed.by Joshua Peters.M.Eng

Microwave device characterization

Master'sMASTER OF ENGINEERIN

Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano

Signal and power integrity co-simulation using the multi-layer finite difference method

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.Ph.D.Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitarama

Signal Integrity Optimization of RF/Microwave Transmission Lines in Multilayer PCBs

While allowing for flexible trace routing and device miniaturization, multilayer printed circuit boards (PCB) suffer from performance issues at high frequency due to the impedance mismatch caused by vertical transitions. In this paper, a process for optimizing the high-speed performance of microstrip to stripline transitions in multilayer PCBs is demonstrated. This includes strategic tuning of via dimensions using time-domain reflectometry and an analysis of the use of shielding vias to prevent parasitic cavity resonance. Simulations of optimized 2-layer, 4-layer, and 6-layer microstrip to stripline transitions show a return loss of 20 dB up to 7 GHz. To demonstrate a useful microwave application, a planar filter with a passband of 4 GHz to 6 GHz is submerged 6-layers. The simulation shows that when paired with the optimized vertical transitions, the filter can maintain performance