Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

In this paper, we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in CS CMOS image sensors are recursive pseudo-random binary matrices. We have proved that the restricted isometry property of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random number generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behavior that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber reconstruction algorithm. By means of single value decomposition, we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N000141410355European Union H2020 76586

Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device

Energy-Aware Low-Power CMOS LNA with Process-Variations Management

A reconfigurable low-noise amplifier (LNA) with digitally controllable gain and power consumption is presented.This architecture allows increasing power consumption only when required, that is, to improve LNA’s radiofrequency performance at extreme communication-channel conditions and/or to counteract the effect of process, voltage, and temperature variations.The proposed design leads to significant power saving when a relaxed operation is acceptable. The LNA is implemented in a 130nm 1.2V CMOS technology for a 2.4GHz IEEE-802.15.4 application. Simulated LNAperformance (taking into account theworst cases under process variations) is comparable to recently published worksCAPES-Brazil 176/12Ministerio de Asuntos Exteriores y Cooperación D/024124/09Junta de Andalucía P09-TIC- 5386Ministerio de Economía y Competitividad TEC2011-2830

Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field

Using Modified Bessel Functions for Analysis of Nonlinear Effects in a MOS Transistor Operating in Moderate Inversion

This work was supported in part by the NSERC, Canada, in part by the Portuguese Foundation for Science and Technology under Project PESTOEEEI/UI0066/2015 and foRESTER Project PCIF/SSI/0102/2017, and in part by the Academy of Finland.This paper describes analysis of nonlinear effects in a MOS transistor operating in moderate inversion and saturation. The dependence of the drain current on the gate-source and drain-source voltages is described using a modified version of the 'reconciliation' model developed by Y. Tsividis. In the new model, the current components, which correspond to the terms depending exponentially on normalized gate-source or drain-source modulating sinusoidal voltages, are presented using modified Bessel functions. This approach allows one to find the first, second, and third harmonics of the drain current caused by the gate-source or drain-source voltage sinusoidal modulation and find also the intermodulation terms produced by these two modulating voltages. The results are applied to set the requirements to the gate-source and drain-source bias voltages in design of low-distortion and/or low-voltage amplifiers. It is shown that the realization of the stage with the zero value of third-order harmonic requires extremely tight tolerances for the threshold voltage. The suppression of intermodulation terms requires increased drain-source voltage. These recommendations are confirmed by simulations.authorsversionpublishe

FPGA Implementation of Real-Time Compressive Sensing with Partial Fourier Dictionary

This paper presents a novel real-time compressive sensing (CS) reconstruction which employs high density field-programmable gate array (FPGA) for hardware acceleration. Traditionally, CS can be implemented using a high-level computer language in a personal computer (PC) or multicore platforms, such as graphics processing units (GPUs) and Digital Signal Processors (DSPs). However, reconstruction algorithms are computing demanding and software implementation of these algorithms is extremely slow and power consuming. In this paper, the orthogonal matching pursuit (OMP) algorithm is refined to solve the sparse decomposition optimization for partial Fourier dictionary, which is always adopted in radar imaging and detection application. OMP reconstruction can be divided into two main stages: optimization which finds the closely correlated vectors and least square problem. For large scale dictionary, the implementation of correlation is time consuming since it often requires a large number of matrix multiplications. Also solving the least square problem always needs a scalable matrix decomposition operation. To solve these problems efficiently, the correlation optimization is implemented by fast Fourier transform (FFT) and the large scale least square problem is implemented by Conjugate Gradient (CG) technique, respectively. The proposed method is verified by FPGA (Xilinx Virtex-7 XC7VX690T) realization, revealing its effectiveness in real-time applications

Estudio e implementación de algoritmos de fusión sensorial para sensores pulsantes y clásicos con protocolo AER de comunicación y aplicación en sistemas robóticos neuroinspirados

The objective of this thesis is to analyze, design, simulate and implement a model that follows the principles of the human nervous system when a reaching movement is made. The background of the thesis is the neuromorphic engineering field. This term was first coined in the late eighties by Caver Mead. Its main objective is to develop hardware devices, based on the neuron as the basic unit, to develop a range of tasks such as: decision making, image processing, learning, etc. During the last twenty years, this field of research has gathered a large number of researchers around the world. Spike-based sensors and devices that perform spike processing tasks have been developed. A neuro-inspired controller model based on the classic algorithms VITE and FLETE is proposed in this thesis (specifically, the two algorithms presented are: the VITE model which generates a non-planned trajectory and the FLETE model to generate the forces needed to hold a position reached). The hardware platforms used to implement them are a FPGA and a VLSI multi-chip setup. Then, considering how a reaching movement is performed by humans, these algorithms are translated under the constraints of each hardware device. The constraints are: spike-processing blocks described in VHDL for the FPGA and neurons LIF for the VLSI chips. To reach a successful translation of VITE algorithm under the constraints of the FPGA, a new spike-processing block is designed, simulated and implemented: GO Block. On the other hand, to perform an accurate translation of the VITE algorithm under VLSI requirements, the recent biological advances are studied. Then, a model which implements the co-activation of NMDA channels (this activity is related to the activity detected in the basal ganglia short time before a movement is made) is modeled, simulated and implemented. Once the model is defined for both platforms, it is simulated using the Matlab Simulink environment for FPGA and Brian simulator for VLSI chips. The hardware results of the algorithms translated are presented. The open-loop spike-based VITE (on both platforms) and closed-loop (FPGA) applied and connected to a robotic platform using the AER bus show an excellent behaviour in terms of power and resources consumption. They show also an accurate and precise functioning for reaching and tracking movements when the target is supplied by an AER retina or jAER. Thus, a full neuro-inspired architecture is implemented: from the sensor (retina) to the end effector (robot) going through the neuro-inspired controller designed. An alternative for the SVITE platform is also presented. A random element is added to the neuron model to include variability in the neural response. The results obtained for this variant, show a similar behaviour if a comparison with the deterministic algorithms is made. The possibility to include this pseudo-random controller in noise and / or random environment is demonstrated. Finally, this thesis claims that PFM is the most suitable modulation to drive motors in a neuromorphic hardware environment. It allows supplying the events directly to the motors. Furthermore, it is achieved that the system is not affected by spurious or noisy events. The novel results achieved with the VLSI multi-chip setup, this is the first attempt to control a robotic platform using sub-thresold low-power neurons, intended to set the basis for designing neuro-inspired controllers

SMARAD - Centre of Excellence in Smart Radios and Wireless Research - Activity Report 2011 - 2013

Centre of Excellence in Smart Radios and Wireless Research (SMARAD), originally established with the name Smart and Novel Radios Research Unit, is aiming at world-class research and education in Future radio and antenna systems, Cognitive radio, Millimetre wave and THz techniques, Sensors, and Materials and energy, using its expertise in RF, microwave and millimeter wave engineering, in integrated circuit design for multi-standard radios as well as in wireless communications. SMARAD has the Centre of Excellence in Research status from the Academy of Finland since 2002 (2002-2007 and 2008-2013). Currently SMARAD consists of five research groups from three departments, namely the Department of Radio Science and Engineering, Department of Micro and Nanosciences, and Department of Signal Processing and Acoustics, all within the Aalto University School of Electrical Engineering. The total number of employees within the research unit is about 100 including 8 professors, about 30 senior scientists and about 40 graduate students and several undergraduate students working on their Master thesis. The relevance of SMARAD to the Finnish society is very high considering the high national income from exports of telecommunications and electronics products. The unit conducts basic research but at the same time maintains close co-operation with industry. Novel ideas are applied in design of new communication circuits and platforms, transmission techniques and antenna structures. SMARAD has a well-established network of co-operating partners in industry, research institutes and academia worldwide. It coordinates a few EU projects. The funding sources of SMARAD are diverse including the Academy of Finland, EU, ESA, Tekes, and Finnish and foreign telecommunications and semiconductor industry. As a by-product of this research SMARAD provides highest-level education and supervision to graduate students in the areas of radio engineering, circuit design and communications through Aalto University and Finnish graduate schools. During years 2011 – 2013, 18 doctor degrees were awarded to the students of SMARAD. In the same period, the SMARAD researchers published 197 refereed journal articles and 360 conference papers