14 research outputs found

    Translation Lookaside Buffer on the 65-nm STG DICE Hardened Elements

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    This paper presents the design of hardened translation lookaside buffer based on Spaced Transistor Groups (STG) DICE cells in 65-nm bulk CMOS technology. The resistance to impacts of single nuclear particles is achieved by spacing transistors in two groups together with transistors of the output combinational logic. The elements contain two spaced identical groups of transistors. Charge collection from particle tracks by only transistors of just one of the two groups doesn’t lead to the cell upset. The proposed logical element of matching based on the STG DICE cell for a content-addressable memory was simulated using TCAD tool. The results show the resistance to impacts of single nuclear particles with linear energy transfer (LET) values up to 70 MeV×cm2/mg. Short-term noise pulses in combinational logic of the element can be observed in the range of LET values from 20 to 70 MeV×cm2/mg

    0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance

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    This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz.Accepted versio

    DESIGN AND SYNTHESIS OF HIGH DENSITY INTEGRATED CIRCUITS

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    Gordon E. Moore, a co-founder of Fairchild Semiconductor, and later of Intel, predicted that after 1980 the complexity of an Integrated Circuit would be expected to double every two years. The prevision made by Moore held for decades, for this reason it is also called \u201cMoore\u2019s law\u201d. The trend in ICs is driven by a reduction of area and power consumption. Today scaled CMOS technologies are the main solution for digital processing. However, the interconnection scaling is not optimal. At every new technology node, the number of metal layers and their thickness increases, exploiting the vertical direction. The reduction of the minimum distance between interconnections and the growth in vertical dimension increase the parasitic capacitance and consequently the dynamic power consumption. Moreover, due to the non-optimal scaling of the interconnections, signal routing is becoming more and more challenging at every technology node advancement. Very scaled technologies make possible to reach a great transistor density. However, the design must comply to strict rules for metal interconnections. The aim of this thesis is to find possible solutions to the disadvantages of scaled CMOS technologies. This goal is obtained in two different ways: using ad-hoc design techniques on today CMOS technologies and finding new approaches to logic synthesis of nanocrossbars, that are an emerging post-CMOS technology. The two approaches used corresponds to the two parts of this thesis. The first part presents the design of an Associative Memory focusing the attention on develop design and logic synthesis techniques to reduce power consumption. The field of applicability of AMs is real-time pattern-recognition tasks. The possible uses range from scientific calculations to image processing for intelligent autonomous devices to image reconstruction for electro-medical apparatuses. In particular AMs are used in High Energy Physics (HEP) experiments to detect particle tracks. HEP experiments generate a huge amount of data, but it is necessary to select and save only the most interesting tracks. Being the data compared in parallel, AMs are synchronous ICs that have a very peaked power consumption, and therefore it is necessary to minimize the power consumption. This AM is designed within the projects IMPART and HTT in 28 nm CMOS technology, using a fully-CMOS approach. The logic is based on the propagation of a \u201ckill signal\u201d that, if one of the bits in a word is not matching, inhibits the switching of the following cells. Thanks to this feature, the designed AM array consumes less than 0.7 fJ/bit. A prototype has been fabricated and it has proven to be functional. The final chip will be installed in the data acquisition chain of ATLAS experiment on HL-LHC at CERN. In the future nanocrossbars are expected to reduce device dimensions and interconnection complexity with respect to CMOS. Logic functions are obtained with switching lattices of four-terminal switches. The research activity on nanocrossbars is done within the project NANOxCOMP. To improve synthesis are used some algorithmic approaches based on Boolean function decomposition and regularities, in particular P-circuits, EXOR-Projected Sums of Products (EP-SOP), Dimension-reducible (D-red) functions and autosymmetric functions. The decomposed functions are implemented into lattices using internal and external decomposition methods. Experimental results show that this approaches reduce the complexity of the single synthesis problem and leads, in average, to a reduction of lattice area and synthesis time. Lattices are made of self-assembled structures and they have a non-negligible defectivity ratio. To cope with this limitation, some techniques to reduce sensitivity to defects have been studied

    RFID Technology in Intelligent Tracking Systems in Construction Waste Logistics Using Optimisation Techniques

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    Construction waste disposal is an urgent issue for protecting our environment. This paper proposes a waste management system and illustrates the work process using plasterboard waste as an example, which creates a hazardous gas when land filled with household waste, and for which the recycling rate is less than 10% in the UK. The proposed system integrates RFID technology, Rule-Based Reasoning, Ant Colony optimization and knowledge technology for auditing and tracking plasterboard waste, guiding the operation staff, arranging vehicles, schedule planning, and also provides evidence to verify its disposal. It h relies on RFID equipment for collecting logistical data and uses digital imaging equipment to give further evidence; the reasoning core in the third layer is responsible for generating schedules and route plans and guidance, and the last layer delivers the result to inform users. The paper firstly introduces the current plasterboard disposal situation and addresses the logistical problem that is now the main barrier to a higher recycling rate, followed by discussion of the proposed system in terms of both system level structure and process structure. And finally, an example scenario will be given to illustrate the system’s utilization

    Proceedings of the 11th International Conference on Kinanthropology

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    The 11th International Conference on Kinantropology was held on the Nov 29 – Dec 1, 2017 in Brno and was organized by the Faculty of Sports Studies, Masaryk University and the Faculty of Kinesiology, University of Zagreb. This year was divided into several themes: sports medicine, sport and social science, sport training, healthy lifestyle and healthy ageing, sports management, analysis of human movement. Part of the conference was also a symposium Atletika and Ortoreha that gathered specialists in physiotherapy

    Active production of large aspheric optics for astronomy

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    This thesis is devoted mainly to tackling the unsolved problem of producing secondary mirrors for 8 m telescopes, which will be up to 2-2.5 m in diameter and in excess of 1000 waves aspheric. This cannot be done by traditional methods. The project directly addresses the problem and forms part of the UK's R and D contributions to the Gemini USA/UK/Canada/Brazil/Chile/Argentina project to produce two 8 m telescopes. Its aim was to develop a new active method. The thesis starts with a review of astronomical implications of 8 m telescope projects currently being undertaken or planned worldwide and continues with discussions on technological challenges specifically in main optics production. The first stage of producing the mirror is generation of the aspheric surface profile by diamond milling. This has been directly addressed by developing a new computer-controlled profiler based on the existing manual hardware of the Grubb-Parsons 2.5 m machine. An essential part of the development also includes a computer controlled contact profilometer. The system performance is presented, including calibration, error profile and convergence of error compensation. The main part of the project was to develop polishing using a full size active lap, by which the pressure distribution and hence ablation rate are modulated in real time. The progress of the project is described, starting with a review of other approaches being developed world wide. The overall philosophy and design of active components are presented. Following this, experiments with a sub-diameter polisher and a prototype active lap of 85 cm in diameter, as built, are also described, including methods of testing, ablation algorithm and control theory. The final part of this section discusses the performance of the active polishing lap in terms of functionality at component and system levels. The conclusion briefly summarises the evaluation of the active method and its impact on large optics production. It also gives ideas for future improvements of performance, research work still needed and viable applications for the technique
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