Hard-switched switched capacitor converter design

Switched capacitor (SC) converters are becoming quite popular for use in DC-DC power conversion. The concept of equivalent resistance in SC converters is frequently used to determine the conduction losses due to the load current. A variety of methodologies have been presented in the literature to predict the equivalent resistance in hard-switched SC converters. However, a majority of the methods described are difficult to apply to general SC converter topologies. Additionally, previous works have not considered all nonidealities in their analysis, such as switching losses or stray inductances. This work presents a generalized and easy to use model to determine the equivalent resistance of any high-order SC converter. The presented concepts are combined to derive a complete loss model for SC converters. The challenges of implementing output voltage regulation are addressed as well. A current-fed SC topology is presented in this work that overcomes the problems associated with voltage regulation. The new topology opens up a variety of additional operating modes, such as power sharing. These additional operating modes are explored as well. The presented concepts are verified using digital simulation tools and prototype converters. --Abstract, page iii

Dual-Input Switched Capacitor Converter Suitable for Wide Voltage gain Range

International audienceThe capacitive-based switching converter suffers from low efficiency, except for a few conversion ratios, thus limiting its use in fine dynamic voltage and frequency scaling for the power management of digital circuits. Therefore, this paper proposes a Multiple Input Single Output Switched Capacitor Converter (MISO-CSC) to provide flatness efficiency over a large voltage gain range. First, the power efficiency calculation in MISO configuration is given, and then the best ones to optimize the number of switched capacitor structures is selected. By using two power supplies, the MISO converter produces 18 ratios instead of three in SISO (Single Input Single Output) mode. Using a CMOS 65nm technology, the transistor-based simulations exhibit an average 15% efficiency gain over a 0.5-1.4V output voltage range compared to the SISO-CSC. Index Terms— switched capacitor converter, multi-input converter, power efficiency optimization, fully integrated voltage regulator, dynamic voltage and frequency scaling

Efficiency Theory of switched capacitors converter

National audienceThis paper reports on a theoretical study of the efficiency of a switched capacitor converter for autonomous sensors. The sensor is composed of an energy harvester (Solar cell), the electronic system (micro-controller, radio, temperature sensor, MEMS. . . ) and a battery. Based on our theory, we calculate this efficiency with respect to: the switching frequency, the capacitance values and the battery voltage. We present this using 3-D graphs. This theory is based on Ultra-Low-Power Embedded systems such as wireless sensors with photovoltaic harvesters operating in low-light conditions. In this case, the harvested energy from PV do not exceed a few tens of micro-watts, which forbids the use of "power-hungry" coil-based power converters. On the contrary, using switched capacitors converter is a better alternative for this kind of application. We here present a theoretical framework deriving the maximum efficiency achieved by a switched capacitor converter with respect to: the switching frequency, the capacitance value and the battery voltage

SCC Equivalent Resistance: the Relationship for Complementary Buck and Boost and Accurate Calculation for 2-Phase Converters

This paper makes the following contributions to Switched Capacitor Converter (SCC) equivalent (output) resistance analysis. First, it suggests the relationship between equivalent resistances of complementary buck and boost SCC: equivalent resistance of a boost SCC equals that of its buck counterpart times squared boost voltage Target Ratio (Voltage Conversion Ratio). Another contribution is equivalent resistance accurate calculation methodology for an arbitrary 2-phase SCC

New generation of switched capacitor converters

Author name used in this publication: Cheng K. W. E.Version of RecordPublishe

Design of a bidirectional energy buffer using a switched-capacitor converter and supercapacitors for an auxiliary EIS converter for fuel cell stacks

Fuel cell as an attractive clean energy source has gained a great deal of interest. To increase the durability and reliability of fuel cells, diagnostics systems that can detect degradation and faults inside fuel cell stacks in end applications are highly in need. Electrochemical impedance spectroscopy (EIS), among other methods, is a promising characterizing tool for diagnostics and condition monitoring of fuel cells. It was traditionally only applied to single-cell or short stacks at low-power levels and required special laboratory equipment, but was recently brought to high-power stacks too which was made possible by many technological advancements. This is mainly owing to a growing interest in performing in situ EIS as a non-destructive method without the need for dismantling the stack. Unlike traditional approaches which relied on extra equipment, converter-based EIS provides attractive solutions for this purpose. In this thesis, the design and utilization of a bidirectional energy buffer module composed of a switched-capacitor converter (SCC) and a supercapacitor string for a new auxiliary EIS converter solution is presented. The module is designed towards having a more compact auxiliary converter unit. The design of the proposed energy buffer module is investigated in detail and a guideline is provided considering the application-specific optimal conversion ratio, supercapacitor string capacitance, and the probable limitations imposed by high EIS frequencies on certain situations. In a nutshell, the proposed switched-capacitor converter module (SCCM) consists of a bidirectional high voltage-gain SCC connected with supercapacitor string helps with the compactness and miniaturization of the entire auxiliary EIS converter and eliminating the potential problems of electrolytic capacitors such as bulkiness and limited lifetime due to the impact of ripples. The SCCM energy buffer with a high voltage gain offers a high buffering ratio for utilizing supercapacitors as the energy storage device

Adaptive Processes in Hearing

Our auditory environment is constantly changing and evolving over time, requiring us to rapidly adapt to a complex dynamic sensory input. This adaptive ability of our auditory system can be observed at different levels, from individual cell responses to complex neural mechanisms and behavior, and is essential to achieve successful speech communication, correct orientation in our full environment, and eventually survival. These adaptive processes may differ in individuals with hearing loss, whose auditory system may cope via “readapting” itself over a longer time scale to the changes in sensory input induced by hearing impairment and the compensation provided by hearing devices. These devices themselves are now able to adapt to the listener’s individual environment, attentional state, and behavior. These topics related to auditory adaptation, in the broad sense of the term, were central to the 6th International Symposium on Auditory and Audiological Research held in Nyborg, Denmark, in August 2017. The symposium addressed adaptive processes in hearing from different angles, together with a wide variety of other auditory and audiological topics. The papers in this special issue result from some of the contributions presented at the symposium

Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade

The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker. The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-PT track candidates. The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version