7,243 research outputs found
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Benchmarking for high-level synthesis
This paper discusses issues in benchmarking for synthesis, and suggests techniques for the comparison of benchmark descriptions, the synthesis tools used, as well as the synthesized designs finally generated. We propose a classification scheme for the assumptions made for the comparison of different synthesis tools, and present an Assumptions Chart that can be used to visualize different benchmarks, tools and synthesis results. We illustrate application of this Assumptions Chart using synthesis experiments that were conducted on some sample High-Level Synthesis Workshop bench-marks
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Timing models for high-level synthesis
In this paper, we describe a timing model for clock estimation during high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers all delay elements, including datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices must be rapidly and incrementally calculated
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Layout area models for high-level synthesis
Traditionally, the common cost functions, the number of functional units, registers and selector inputs, are used in high level synthesis as quality measures. However, these traditional design quality measures may not reflect the real physical design. To establish quality measures based on the physical designs, we propose layout estimation models for two commonly used data path and control layout architectures. The results show that quality measures deriving from our models give an accurate prediction of the final layout. The results also show that traditional cost functions are not good indicators for optimization in high level synthesis
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Layout-driven allocation for high level synthesis
We propose a hypergraph model and a new algorithm for hardware allocation. The use of a hypergraph model facilitates the identification of sharable resources and the calculation of interconnect costs. Using the hyper graph model, the algorithm performs interconnect optimization by taking into account interdependent relationships between three allocation subtasks: register, operation, and interconnect allocations simultaneously. Previous algorithms considered these three tasks serially. Another novel contribution of our algorithm is the exploration of design space by trading off storage units and interconnects. We also demonstrate that traditional cost functions using the number of registers and the number of mux-inputs can not guarantee the minimal area. To rectify the problem, we introduce a new layout area cost function and compare it to the traditional cost functions. Our experiments show that our algorithm is superior to previously published algorithms under traditional cost functions
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Bridging high-level synthesis to RTL technology libraries
The output of high-level synthesis typically consists of a netlist of generic RTL components and a state sequencing table. While module generators and logic synthesis tools can be used to map RTL components into standard cells or layout geometries, they cannot provide technology mapping into the data book libraries of functional RTL cells used commonly throughout the industrial design community. In this paper, we introduce an approach to implementing generic RTL components with technology-specific RTL library cells. This approach addresses the criticism of designers who feel that high-level synthesis tools should be used in conjunction with existing RTL data books. We describe how GENUS, a library of generic RTL components, is organized for use in high-level synthesis and how DTAS, a functional synthesis system, is used to map GENUS components into RTL library cells
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GENUS : a generic component library for high level synthesis
This report describes the organization of GENUS, a generic component library for high level synthesis. Generic components and instances in GENUS are organized into hierarchical classes, with the component type stored at the root of the hierarchy, and particular instances stored at the leaves. This permits a consistent representation of generic components which may be used by a variety of synthesis and analysis tools. The appendix contains the description of the GENUS generator library
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