Devos, Harald

Stroobandt, Dirk

English

Ghent University Academic Bibliography

High-level Synthesis for Data-intensive ApplicationsHarald Devos and Dirk Stroobandt∗Electronics and Information Systems Department (ELIS)Ghent University, BelgiumHarald.Devos@elis.UGent.be1. INTRODUCTIONMost high-level synthesis tools focus on exploiting parallelism.However, for data-intensive applications the memory bandwidth orlatency may become a bottleneck and improving data access pat-terns becomes as important as exploiting parallelism. To minimizethe number of accesses to off-chip memory, a memory hierarchyis needed to reuse data in on-chip memories. The resulting perfor-mance heavily depends on the locality of the data accesses. Looptransformations are a means to improve this locality but also mayhave a large impact on the loop control complexity and thus on thecontrol hardware. A close integration of loop transformations andhardware generation is needed to tackle this problem.We present a methodology, supported by tools, to explore looptransformation variants and study their impact on both data ac-cess patterns and generated control hardware. The construction ofan application-specific memory system is supported, which offersmore than solely a reduction of bandwidth requirements.2. LOOP TRANSFORMATIONSA part of a program where the control flow is independent of theprocessed data is called a SCoP (Static Control Part), and can berepresented in a polyhedral model [6]. Loop transformations arenow reduced to matrix and vector operations. This representationovercomes a lot of limitations of syntactic representations and fa-cilitates the composition of a long sequence of transformations [6].For guiding the composition of loop transformation sequenceswe make use of SLO (Suggestions for Locality Optimizations) [2,4]. This tool investigates the data reuses within a program execu-tion and gives hints for potential optimizing loop transformations.3. LOOP CONTROLLER VARIANTSWe have extended CLooG [1], a library generating software codefrom a polyhedral representation of a SCoP (without statement in-formation), towards CLooGVHDL generating synthesizable VHDLdescriptions of hardware controller blocks.∗This research is supported by the I.W.T. grant 060068 and theF.W.O. grant G.0475.05.Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission and/or a fee.DAC HLS workshop ’08 Anaheim, California USACopyright 200X ACM X-XXXXX-XX-X/XX/XX ...$5.00.CLooG has a number of code generation optimization optionswhich also have a large influence on the generated hardware con-trollers. Next to this, the generated architecture offers several op-tions to trade off area, clock frequency and cycle count of an im-plementation as demonstrated in [3].4. APPLICATION-SPECIFIC MEMORYSYSTEMFor processors, optimizations are done for a fixed memory hi-erarchy, while on FPGAs or ASICs the memory structure can bemade application-specific. Furthermore, buffer memories not onlyreduce the number of off-chip accesses or hide the external mem-ory latency but can also augment the on-chip bandwidth throughparallel access of multiple buffers or simplify address expressionsby remapping data [5]. The final target, i.e. fully automatic gener-ation of the optimal memory system for a given application, withdata mapping and scheduling of burst transfers, will probably notbe reached in the near future. However, many useful techniqueshave been developed in the context of software but are not inte-grated yet with HLS tools. In the mean time, we offer a step-by-step methodology to construct such a memory system directed bythe user. Special care is taken of the reusability of design modulesand the simplification of addresses to improve the performance.5. REFERENCES[1] C. Bastoul. Code generation in the polyhedral model is easierthan you think. In PACT’13 IEEE International Conference onParallel Architecture and Compilation Techniques, pages7–16, Juan-les-Pins, September 2004.[2] K. Beyls. SLO – Suggestions for Locality Optimizations.http://slo.sourceforge.net/.[3] H. Devos. Loop Transformations for the OptimizedGeneration of Reconfigurable Hardware. PhD thesis, GhentUniversity, February 2008.[4] H. Devos, K. Beyls, M. Christiaens, J. Van Campenhout, E. H.D’Hollander, and D. Stroobandt. Finding and applying looptransformations for generating optimized FPGAimplementations. Trans. on High Performance EmbeddedArchitectures and Compilers I, LNCS, 4050:159–178, 2007.[5] H. Devos, D. Stroobandt, and J. Van Campenhout. Building anapplication-specific memory hierarchy on FPGAs. In 2ndHiPEAC Workshop on Reconfigurable Computing, pages53–62, Göteborg, Sweden, January 2008.[6] S. Girbal, N. Vasilache, C. Bastoul, A. Cohen, D. Parello,M. Sigler, and O. Temam. Semi-automatic composition ofloop transformations for deep parallelism and memoryhierarchies. Int. J. Parallel Program., 34(3):261–317, 2006.

High-level synthesis for data-intensive applications

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High-level synthesis for data-intensive applications

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