Functional Verification of Power Electronic Systems

This project is the final work of the degree in Industrial Electronics and Automatic Engineering. It has global concepts of electronics but it focuses in power electronic systems. There is a need for reliable testing systems to ensure the good functionality of power electronic systems. The constant evolution of this products requires the development of new testing techniques. This project aims to develop a new testing system to accomplish the functional verification of a new power electronic system manufactured on a company that is in the power electronic sector . This test system consists on two test bed platforms, one to test the control part of the systems and the other one to test their functionality. A software to perform the test is also designed. Finally, the testing protocol is presented. This design is validated and then implemented on a buck converter and an inverter that are manufactured at the company. The results show that the test system is reliable and is capable of testing the functional verification of the two power electronic system successfully. In summary, this design can be introduced in the power electronic production process to test the two products ensuring their reliability in the market

Photoheliograph Functional Verification Unit Test and Operations Plan, November 1967 - June 1968

Test and operations plan for functional verification unit of photoheliograph to be used with Apollo telescope moun

Are IEEE 1500 compliant cores really compliant to the standard?

Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suit

Functional Verification through Operation Diagnostics

One of the core objectives of the commissioning process is to ensure that the dynamic systems function correctly. Just as important, if not more so, is enabling the correct function of those systems throughout occupancy. While verification strategies vary, it is clear that examination of actual operation produces the most accurate results. This is accomplished through trend logging. With analysis of regularly recorded control point data through visualization (including graphs, charts, etc.), a quick and accurate diagnosis of incorrect or less than optimal operation can be assessed. However, several questions arise regarding this process: What data should be visualized? What form should this visualization take? How can data from several different yet interrelated control points be best compared? Finally, what patterns within a visualization should be sought

Functional Verification of Processor Execution Units

Práce se zaobírá začleněním procesu funkční verifikace do vývojového cyklu návrhu funkčních jednotek v prostředí pro souběžný návrh hardwaru a softwaru systému Codasip. Cílem bylo navrhnout a implementovat verifikační prostředí v jazyku SystemVerilog pro verifikaci automaticky generované hardwarové reprezentace těchto jednotek. Na začátku jsou rozebrány přínosy a obvyklé postupy při funkční verifikaci a vlastnosti systému Codasip.  Dále je v práci popsán návrh, implementace, analýza průběhu a výsledků testů verifikace simulačního modelu aritmeticko-logické jednotky. Závěrem jsou zhodnoceny dosažené výsledky práce a navrhnuta zlepšení pro možný další rozvoj verifikačního prostředí.The thesis deals with integration of functional verification into the design cycle of execution units in  a hardware-software co-design environment of the Codasip system. The aim of the thesis is to design and implement a verification environment in SystemVerilog in order to verify automatically generated hardware representation of the execution units. In the introduction, advantages and basic methods of functional verification and principles of the Codasip system are discussed. Next chapters describe the process of design and implementation of the verification environment of arithmetic-logic unit as well as the analysis of the results of verification. In the end, a review of accomplished goals and the suggestions for future development of the verification environment are made.

Hardware Accelerated Functional Verification of Processor

Mezi aktuálně používané verifikační přístupy patří funkční verifikace. Při funkční verifikaci se ověřuje korektnost implementace počítačového systému vzhledem k specifikaci. Slabým místem v rámci přístupu funkční verifikace je její časová náročnost, na kterou má vliv pomalá softwarová simulace implicitně paralelních hardwarových systémů. V této práci je představeno řešení využívající hardwarovou akceleraci funkční verifikace procesoru. Úvodní kapitoly tvoří teoretický základ pro následující kapitoly, ve kterých se nachází analýza a výběr řešení, návrh verifikačního prostředí a implementační detaily. Závěr práce obsahuje testování výsledného produktu, zhodnocení výsledků práce a vyhlídky do budoucna.Functional verification belongs among the current verification approaches. Functional verification checks the correctness of the implementation of the system, due to its specification. The weakness of the functional verification approach is time consumption caused by slow software simulation of implicitly parallel hardware systems. This paper presents a solution for using a hardware accelerated functional verification of the processor. The introductory chapters form the theoretical basis for the following chapters, that include a choice of solutions, an analysis, a design of a verification environment and implementation details. The conclusion includes tests of the final product, evaluation of the results and the future work perspectives.