On the number of generators for transeunt triangles

This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Discrete Applied Mathematics, 108, 2001, pp. 309-316A transeunt triangle for size n consists of (n+1)x(n+1)x(n+1) 0's and 1's whose values are determined by the sum modulo 2 of two other local values. For a given n, two transeunt triangles of size n can be combined using the element-by-element modulo 2 sum to generate a third transeunt triangle. We show that, for large n ..

On the use of transeunt triangles to synthesize fixed-polarity Reed-Muller expansions of functions

This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Proceedings of the Reed-Muller Workshop 2009, May 23-24, 2009, Naha. Okinawa, Japan, 119-126The transeunt triangle was originally proposed by Suprun as the basis of an algorithm for synthesizing fixed-polarity Reed-Muller (FPRM) expansions of symmetric functions. However, he provided no proof that this technique produced the correct FPRM expansion. We provide such a proof, thus establishing the validity of the transeunt triangle technique. Further, we show the extent to which the transeunt triangle reduces the computational work needed. Because of the efficiency of the transeunt triangle, we are able to do experimental studies on sets of n-variable symmetric functions for large values of n never before achievable. For example, we show that a surprisingly large percentage of symmetric functions (35% for large n) are optimally realized by just two (of n+1) polarities. This is verified by exhaustive enumeration of symmetric functions with up to 31 variables and by large sample sets (1,000,000) of symmetric functions with up to 100 variables. This suggests that even greater efficiency can be achieved through a heuristic that restricts the polarities to one or both of the favored polarities

Comments on Sympathy: Fast exact minimization of fixed polarity Reed-Muller expansion for symmetric functions

This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.IEEE Trans. On Computer-Aided Design, Vol. 19, No. 11, Nov 2000, pp. 1386-1388The above paper finds an optimal fixed-polarity Reed-Muller expansion of an n-variable totally symmetric function using an OFDD-based algorithm that requires ..

A Method to Find the Best Mixed Polarity Reed-Muller Expression Using Transeunt Triangle

This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.5th International Workshop on Applications of Reed-Muller Expansion in Circuit Design (RM), Starkville, MS, August 2001, pp. 82-93In this paper, we use the transeunt triangle in an efficient algorithm to find the minimum mixed polarity Reed-Muller expression of a given function. This algorithm runs in O (n to the 3rd) time and uses O (n to the 3rd) storage space. We demonstrate this algorithm on benchmark functions, and we extend it to multi-output functions

Logic Design of NanoICS

Today's engineers will confront the challenge of a new computing paradigm, relying on micro- and nanoscale devices. Logic Design of NanoICs builds a foundation for logic in nanodimensions and guides you in the design and analysis of nanoICs using CAD. The authors present data structures developed toward applications rather than a purely theoretical treatment. Requiring only basic logic and circuits background, Logic Design of NanoICs draws connections between traditional approaches to design and modern design in nanodimensions. The book begins with an introduction to the directions and basic methodology of logic design at the nanoscale, then proceeds to nanotechnologies and CAD, graphical representation of switching functions and networks, word-level and linear word-level data structures, 3-D topologies based on hypercubes, multilevel circuit design, and fault-tolerant computation in hypercube-like structures. The authors propose design solutions and techniques, going beyond the underlying technology to provide more applied knowledge. This design-oriented reference is written for engineers interested in developing the next generation of integrated circuitry, illustrating the discussion with approximately 250 figures and tables, 100 equations, 250 practical examples, and 100 problems. Each chapter concludes with a summary, references, and a suggested reading section.Ye

The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model

This paper is a continuation of the study of Neural-Like Networks (NLNs) for computation of Multiple-Valued Logic (MVL) functions. NLN is defined as a feedforward network with no learning. In contrast to classical neural network with Threshold Gates (TGs), the proposed NLN is built of so-called Neuron-Like Gates (NLGs). It was shown in our previous study that NLG is modelled by a Linear Arithmetical expression (LAR). In this paper we show even more simple NLG model. We have developed two word-level models, Linear Weighted Logic expressions (LWLs) and a corresponding set of Linear Decision Diagrams (LDDs). We compare the LWL- and LAR-based NLNs. The experimental study on large MVL circuits shows that the number of nodes in the LDDs derived from LWLs is four times less in average compared to those derived from LARs. They are also 2-7 times more compact (require less memory to store the terminal values).