Improving the hardware complexity by exploiting the reduced dynamics-based fractional order systems

Fractional calculus is nding increased usage in the modeling and control of nonlinear systems with the enhanced robustness. However, from the implementation perspectives, the simultaneous modeling of the systems and the design of controllers with fractional-order operators can bring additional advantages. In this paper, a fractional order model of a nonlinear system along with its controller design and its implementation on a eld programmable gate array (FPGA) is undertaken as a case study. Overall, three variants of the controllers are designed, including classical sliding mode controller, fractional controller for an integer model of the plant, and a fractional controller for a fractional model of the plant (FCFP). A high-level synthesis approach is used to map all the variants of the controllers on FPGA. The integro-differential fractional operators are realized with in nite impulse response lters architecturally implemented as cascaded secondorder sections to withstand quantization effects introduced by xed-point computations necessary for FPGA implementations. The experimental results demonstrate that the fractional order sliding mode controllerbased on fractional order plant (FCFP) exhibits reduced dynamics in sense of fractional integration and differentials. It is further veri ed that the FCFP is as robust as the classical sliding mode with comparable performance and computational resources

Switch based high cardinality node detection

The detection of supernodes with high cardinality is of interest for network monitoring and security. Existing schemes for supernode detection rely on data structures that are independent of the switching functions. This means that for each packet that traverses the switch, both the switching table and the supernode detection structure have to be checked which requires significant memory bandwidth. This can create a bottleneck and reduce the speed of the switch, especially for software implementations. In this letter, a scheme that performs supernode detection as part of Ethernet switching and does not require additional memory accesses nor separated data structures is presented. The scheme has been implemented and compared with the existing methods. The results show that the proposed scheme can reliably identify supernodes while providing a speed up of more than 15% when compared with the existing solutions.This work was supported in part by the Higher Education Commission (HEC) Pakistan and the Ministry of Planning, Development and Special Initiatives under National Centre for Cyber Security; in part by the ACHILLES Project PID2019-104207RB-I00 and the Go2Edge network RED2018-102585-T funded by the Spanish Ministry of Science and Innovation; and in part by the Madrid Community Research Project TAPIR-CM under Grant P2018/TCS4496

Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Reed–Solomon erasure codes (RS-ECs) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a field-programmable gate array (FPGA) in a space platform, it will suffer single-event upsets (SEUs) that can cause failures. In this article, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memory is first studied. Then, a fault detection and location scheme is proposed based on partial reencoding for the faults in the user memory of the RS-EC decoder. Furthermore, check bits are added in the generator matrix to improve the fault location performance. The theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability. Experimental results on a case study show that more than 90% of the faults on user memory could be tolerated by the decoder, and all the other faults can be detected by the fault detection scheme when the number of erasures is smaller than the correction capability of the code. Although false alarms exist (with probability smaller than 4%), they can be used to avoid fault accumulation. Finally, the fault location scheme could accurately locate all the faults. The theoretical estimates are very close to the experiment results, which verifies the correctness of the analysis done.This work was supported in part by the National Natural Science Foundation of China under Grant 61501321, in part by the China Postdoctoral Science Foundation and Luoyang Newvid Technology Company, Ltd., and in part by the ACHILLES Project PID2019-104207RB-I00 funded by the Spanish Ministry of Science and Innovation

VR-ZYCAP: A versatile resourse-level ICAP controller for ZYNQ SOC

This article belongs to the Special Issue Architecture and CAD for Field-Programmable Gate Arrays (FPGAs)Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.This research was funded by Spanish Ministry of Science and Innovation under the ACHILLES project, grant number PID2019-104207RB-I00 and by Taif University Researchers Supporting fund, grant number (TURSP-2020/144), Taif University, Taif, Saudi Arabia

PREVALENCE OF DENGUE VIRAL INFECTION IN PESHAWAR, KPK, PAKISTAN

Background: Dengue is a widespread mosquito-borne viral infection in human beings, which is a major public health concern all over the world. In recent years, dengue is predominant in the tropics and subtropics with a high incidence and increased considerably over the last three decades. Objective: To investigate the prevalence of dengue in Peshawar, Khyber Pakhunkhwa, Province of Pakistan. A total of 823 samples were collected from 823 patients by puncturing the vein in aseptic condition. Serum of patient was analyzed by Immunochromatography technique (ICT). Results: Out of patients, 671 were male and 152 were female. Among the total of 823 samples, 196 (23.81%) patients were positive for Dengue Non-Structure 1 (NS1) while 627 (76.18%) were negative. In male patients 147 (21.90%) were positive for Dengue NS1 while 524 (78.09%) were negative. Out of 152 (18.46%) female patients 49 (32.23%) were positive for Dengue NS1 and remaining 103 (67.76%) were negative. Conclusion: It is concluded that the prevalence of dengue infection is higher in male than in female due to susceptibility of male to certain risk of dengue. Key Words: Prevalence, Dengue viral infection, Peshawa

INCIDENCE OF NEPHROPATHY IN DIABETIC PATIENTS

Objective: To determine the burden of diabetes mellitus (type I and II) and incidence of nephropathy in diabetic patients Peshawar. Methodology: A cross-sectional study carried out on known diabetic patients in Peshawar. This study was conducted on 267 diabetic patients in duration of one year (from January 2018 to February 2019). Both diabetes mellitus type I and type II patients was included in study. Informed consent was taken from all patients before sample collection. Collected samples were further processed in pathology department. Collected data was analyzed by statistical package for social sciences software version 21. Results: Out of total 267 diabetic patients, diabetes mellitus type I was observed in 43 (16.1%) patients while diabetes mellitus type II was examined in 224 (83.9%) patients. The incidence of nephropathy was found in 33 (12.4%) patients with highest percentage in female (57.5%). Conclusion: Diabetes mellitus type II was three times more common than diabetes mellitus type I. Nephropathy incidence is manageable but high risk to female diabetic patients. Key words: Incidence, Nephropathy, Diabetes mellitus, Peshawar

A Novel Homozygous Frameshift Variant in XYLT2 Causes Spondyloocular Syndrome in a Consanguineous Pakistani Family

We report on three new patients with spondyloocular syndrome (SOS) in a consanguineous Pakistani family. All three patients present progressive generalized osteoporosis, short stature, recurrent fractures, hearing loss and visual impairments. WES revealed a novel homozygous frameshift variant in exon 11 of XYLT2 (NG 012175.1, NP_071450.2) resulting in loss of evolutionary conserved amino acid sequences (840 - 865/865) at C -terminus p.R840fs*115. Sanger Sequencing confirmed the presence of the novel homozygous mutation in all three patients while the parents were heterozygous carriers of the mutation, in accordance with an autosomal recessive inheritance pattern. Only nine variants worldwide have previously been reported in XYLT2 in patients with SOS phenotype. These three patients with novel homozygous variant extend the genotypic and phenotypic spectrum of SOS.Peer reviewe