Scattering Parameter Approach to Power MOSFET Design for EMI

Electromagnetic interference (EMI) noise byavalanche oscillations is the major barrier to improve powerdevice performance. Especially the oscillations of three-terminaldevices are more complex than two-terminal devices in point ofthe mutual relationship between devices and external circuit. Scattering parameter (S-parameter) under avalanche condition is obtained to establish stable-unstable criterion with stability factor (K-factor). The stable-unstable criterion clearly indicates the unstable frequency range with each change in MOSFET design. In addition the oscillation mechanism on power MOSFET is modeled with junction capacitance, which is the same as that of diode. For EMI suppression, resonant frequency of external circuit has to be different from unstable frequency of MOSFETs.2012 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD 2012), June 3-7, 2012, Bruges, Belgiu

“Design for EMI Suppression” During Reverse Recovery by 600V Lateral SOI PiN Diode with Traps

PiN diode design for oscillation-induced EMI suppression is proposed with novel structure. The proposed diode is lateral structure with traps using SOI substrate. Conventional PiN diode with vertical structure generates waveform oscillation and the oscillation lower power electronics system reliability. The design of proposed lateral structure with traps will contributes the performance improvement of all of bipolar power devices including IGBT.2014 International Conference on Solid State Devices and Materials, September 8, 2014, Tsukuba International Congress Center, Ibaraki, Japa

Real-time Failure Monitoring System for High Power IGBT Under Acceleration Test Up to 500 A Stress

Real-time failure monitoring system for IGBT module was demonstrated under 500 A power cycling test. The system successfully captured internal phenomena occurred in interface regions of the device under test. Moreover, we proposed realtime failure analysis method by combining the real-time monitoring and image processing techniques. This failure analysis method enables to distinguish the place where degradation occurs in DUT and also trace internal degradation process to failure.2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC\u27s (ISPSD), Jun 15-19, 2014, Hilton Waikoloa Village, Hawaii, US

Ultrafast Lateral 600 V Silicon SOI PiN Diode with Geometric Traps for Preventing Waveform Oscillation

An ultrafast lateral silicon PiN diode with traps is proposed using a silicon-on-insulator (SOI) substrate with traps. The proposed diode successfully suppresses waveform oscillation because the trapped hole suppresses electric field penetration and prevents the oscillation trigger known as “dynamic punch-through.” Because of the short current path caused by the oscillation prevention, the reverse recovery speed was higher and the reverse recovery loss was strongly reduced. The proposed trap structure and design method would contribute to performance improvement of all power semiconductor devices including IGBTs and power MOSFETs

Real Time Monitoring System for Internal Process to Failure of High Power IGBT

A real time failure analysis system for widely used high power IGBT modules is proposed, which enables to inspect internal process to failure of the devices under power stress test as a movie. This system was realized by combining a scanning acoustic tomography (SAT/SAM), power stress controlling, device cooling, water jet system and chip temperature monitoring. This system successfully obtained internal images of a DUT under the load current of 200A.2013 International Conference on Solid State Devices and Materials (SSDM2013), September 24-27, 2013, Hilton Fukuoka Sea Hawk, Fukuoka, Japa

IGBT Avalanche Current Filamentaion Ratio: Precise Simulations on Mesh and Structure Effect

Current filamentaion effect with dynamic avalanche during turn-off transient in IGBT has been discussed for years. In the prior papers, the possibility of device failure has been reported based on TCAD simulation and simulation results have shown that variety of filamentation phenomena exist for conditions assumed in each simulation. It is discussed in this paper, for the first time, that the relationship of filamentation current concentration strength to device design parameters and categorizes filamentation phenomena, introducing current filamentation ratio (CFR). In the paper, guidelines for appropriate mesh pattern selection are also described to ensure the validity of simulation results.ISPSD 2016 28th International Symposium on Power Semiconductor Devices and ICs., Jun 12-16, 2016, Žofín Palace, Prague, Czech Republi

IGBT Avalanche Current Filamentaion Ratio: Precise Simulations on Mesh and Structure Effect

ISPSD 2016 28th International Symposium on Power Semiconductor Devices and ICs., Jun 12-16, 2016, Žofín Palace, Prague, Czech RepublicCurrent filamentaion effect with dynamic avalanche during turn-off transient in IGBT has been discussed for years. In the prior papers, the possibility of device failure has been reported based on TCAD simulation and simulation results have shown that variety of filamentation phenomena exist for conditions assumed in each simulation. It is discussed in this paper, for the first time, that the relationship of filamentation current concentration strength to device design parameters and categorizes filamentation phenomena, introducing current filamentation ratio (CFR). In the paper, guidelines for appropriate mesh pattern selection are also described to ensure the validity of simulation results

Ultra-fast Lateral 600 V Silicon PiN Diode Superior to SiC-SBD

2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), Jun 15-19, 2014, Hilton Waikoloa Village, Hawaii, USAUltra-fast silicon PiN diode is proposed by lateral structure with traps using silicon on insulator (SOI) substrate as shown in Fig. 1. The proposed lateral SOI silicon PiN diode achieved ultra-fast reverse recovery without waveform oscillation successfully. The proposed lateral SOI structure with traps will contributes to performance improvement of all of bipolar power devices including IGBT

Novel 600 V Low Reverse Recovery Loss Vertical PiN Diode with Hole Pockets by Bosch Deep Trench

The performance of a novel diode with characteristic trench shape is predicted by TCAD simulation. A novel 600 V vertical PiN diode with hole pockets by the Bosch deep trench process is proposed for a better trade-off curve between reverse recovery loss and forward voltage. The reverse recovery loss is reduced to a half. In addition, the active chip size of the novel diode is reduced to two-thirds that of the conventional PiN diode in the same forward voltage. The novel diode structure is a strong candidate when the simple fabrication process under development is established.ISPSD 2016 28th International Symposium on Power Semiconductor Devices and ICs., Jun 12-16, 2016, Žofín Palace, Prague, Czech Republi

Eosinophilic Granuloma in a Patient with Marked Improvements of Social Activity as well as Clinical Manifestations

A twenty-year-old male started to have low-back pain. On X-ray survey, unusual shadows of the right humerus and sacrum were found. An open biopsy confirmed a histological diagnosis of eosinophilic granuloma in the 5th lumbal spine and sacrum, followed by the second biopsy of the same diagnosis on the right humerus. A local radiation therapy was performed with 2 Gy for 3 times on the right humerus, along with low-dose continuous cyclophospamide administration for about 17 months. As to pain and performance status (PS) of the patient, there are complete disapperarance of pain and a marked improvement of PS, producing a great success in the therapy and an excellent social life i.e. a good quality of life (QOL) in the present patient