Strong and stable ultraviolet emission from porous silicon prepared by photoetching in aqueous KF solution

A new method of fabricating porous silicon emitting in the ultraviolet (UV) spectral region is presented. This method uses photoetching in an aqueous salt (KF) solution. Strong UV photoluminescence is observed at ～3.3 eV with a full width at a half maximum of ～0.1 eV, which is much narrower than those reported previously. Fourier transform infrared spectroscopy suggests that the surface oxide produced during photoetching plays an important role in the UV emission of the KF-prepared PSi

Structural and photoluminescence properties of porous GaP formed by electrochemical etching

The structural and optical properties of porous GaP have been studied by scanning electron microscopy, spectroscopic ellipsometry, and photoluminescence (PL) spectroscopy. Porous GaP layers were fabricated by anodic etching in HF:H2O:C2H5OH=1:1:2 electrolyte on n-type (100) and (111)A substrates. The morphology of the porous GaP layer is found to depend strongly on the surface orientation. Apart from the red emission band at ～1.7 eV, a supra-band-gap (EgX) emission has been clearly observed on the porous GaP (111)A sample. The anodic porous layer on the (100) substrate, on the other hand, has shown only the red emission at 300 K and both red and green donor-acceptor pair emissions at low temperatures. The correlation between the PL properties and the porous morphology is discussed. An optical transition model is also proposed for the explanation of the PL emission properties of the porous GaP samples

Ultraviolet emission from porous silicon photosynthesized in aqueous alkali fluoride solutions

Stable ultraviolet (UV) photoluminescence (PL) has been observed at room temperature in porous silicon (PSi) fabricated by photoetching in aqueous alkali fluoride solutions. The aqueous solutions used are 1 M NaF and 1 M KF.They give an alkaline reaction caused by partial hydrolysis. The PL peaks at ～3.3 eV have a full width at half maximum of ～0.1 eV, which is much smaller than those reported previously (?0.5 eV). Spectral analyses suggest that both quantum confinement and surface passivation effects enable the observation of UV emission in NaF- and KF-prepared PSi samples

Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length

We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths. The devices consisted of single InGaAs nanowires with a diameter of 30 nm grown on p-type Si(111) substrates. The switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (V-DS) of 0.10 V. Also, pinch-off behavior appeared at moderately low VDS, below 0.10 V. Reducing the channel length of the transistors attained a steep subthreshold slope (< 60 mV/decade) and enhanced the drain current, which was 100 higher than that of the longer channels. (C) 2014 AIP Publishing LLC

Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms

Recent Progress in Vertical Si/III-V Tunnel FETs : From Fundamentals to Current-Boosting Technology

Tunnel field-effect transistors (TFETs) with a steep subthreshold-slope (SS) are promising low-power switches for future large-scale integrated circuits (LSIs) with low power consumption and high performance. Recently, we demonstrated vertical TFETs with III-V/Si heterojunctions. This new sort of tunnel junction achieves a steep SS because of its unique figure-of-merit. Here, we report on recent progress on vertical TFETs using Si/III-V heterojunctions and means for boosting on-state current

Advances in Steep-Slope Tunnel FETs

Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III-V/Si heterojunctions. These heterojunctions, which are formed by direct integration of III-V nanowires (NWs) on Si, are promising tunnel junction for achieving steep subthreshold slope (SS). The III-V/Si heterojunction inherently forms abrupt junctions regardless of precise doping technique because the band discontinuity is determined by only the offset of III-V and Si, and depletion region can be controlled by the III-V MOS structure. Thus, good gate-electrostatic control with a large internal electrical field for modulation of tunnel transport can be achieved. Here we repot on recent advances in the vertical TFETs using the III-V NW/Si heterojunction with surrounding-gate architecture and demonstrate steep-SS behavior and very low parasitic leakage current