Method of producing high T(subc) superconducting NBN films

Thin films of niobium nitride with high superconducting temperature (T sub c) of 15.7 K are deposited on substrates held at room temperature (approx 90 C) by heat sink throughout the sputtering process. Films deposited at P sub Ar 12.9 + or - 0.2 mTorr exhibit higher T sub c with increasing P sub N2,I with the highest T sub c achieved at P sub n2,I= 3.7 + or - 0.2 mTorr and total sputtering pressure P sub tot = 16.6 + or - 0.4. Further increase of N2 injection starts decreasing T sub c

Thin film memory matrix using amorphous and high resistive layers

Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor

Memory switches based on metal oxide thin films

MnO.sub.2-x thin films (12) exhibit irreversible memory switching (28) with an OFF/ON resistance ratio of at least about 10.sup.3 and the tailorability of ON state (20) resistance. Such films are potentially extremely useful as a connection element in a variety of microelectronic circuits and arrays (24). Such films provide a pre-tailored, finite, non-volatile resistive element at a desired place in an electric circuit, which can be electrically turned OFF (22) or disconnected as desired, by application of an electrical pulse. Microswitch structures (10) constitute the thin film element, contacted by a pair of separate electrodes (16a, 16b) and have a finite, pre-selected ON resistance which is ideally suited, for example, as a programmable binary synaptic connection for electronic implementation of neural network architectures. The MnO.sub.2-x microswitch is non-volatile, patternable, insensitive to ultraviolet light, and adherent to a variety of insulating substrates (14), such as glass and silicon dioxide-coated silicon substrates

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier

Cascaded VLSI neural network architecture for on-line learning

High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A comparison-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates

Electronic neural network for solving traveling salesman and similar global optimization problems

This invention is a novel high-speed neural network based processor for solving the 'traveling salesman' and other global optimization problems. It comprises a novel hybrid architecture employing a binary synaptic array whose embodiment incorporates the fixed rules of the problem, such as the number of cities to be visited. The array is prompted by analog voltages representing variables such as distances. The processor incorporates two interconnected feedback networks, each of which solves part of the problem independently and simultaneously, yet which exchange information dynamically

High density associative memory

A multi-layered, thin-film, digital memory having associative recall. There is a first memory matrix and a second memory matrix. Each memory matrix comprises, a first layer comprising a plurality of electrically separated row conductors; a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; and, a plurality of resistance elements electrically connected between the row condutors and the column conductors at respective intersections of the row conductors and the column conductors, each resistance element comprising, in series, a first resistor of sufficiently high ohmage to conduct a sensible element current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross, the second resistor having the quality of breaking down to create a short therethrough upon the application of a breakdown level voltage across the first and second resistors