85 research outputs found
A 0.18µm CMOS DDCCII for Portable LV-LP Filters
In this paper a current mode very low voltage (LV) (1V) and low power (LP) (21 µW) differential difference second generation current conveyor (CCII) is presented. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA) so to design a suitable LV LP integrated version of the so-called differential difference CCII (DDCCII). Post-layout results, using a 0.18µm SMIC CMOS technology, have shown good general circuit performances making the proposed circuit suitable for fully integration in battery portable systems as, for examples, fully differential Sallen-Key bandpass filter
Microwave Active Filter Design
A simplified method for the project and design of microwave active filters is presented here. The presented design is based on the use of an active inductor that emulates an inductor behavior by implementing a passive variable phase- and amplitude-compensating network and amplifiers, forming a gyrator-C architecture. This method can be applied with success for the design of bandpass filters with very high performances in terms of integration and application from a few hundreds of MHz to tens of GHs with filter high dynamic range and frequency tuning capability
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
An IC architecture for RF Energy Harvesting systems
In this work we present an IC architecture for RF energy harvesting. The system has been designed with a 0.18μm CMOS SMIC technology and optimized at 900MHz. Simulation results have confirmed that the integrated system handles an incoming power typically ranging from -25 dBm to 20 dBm by rectifying the variable input signals into a DC voltage source with an overall efficiency up to 50%. The chip area estimation for the proposed system is as low as 3x3mm2
Sustainability of Biogas Based Projects: Technical and Economic Analysis
Biomethane is a renewable gas produced by the transformation of organic matter. It can lead to emissions reduction and it contributes to increasing methane production. Incentive policies favour its development and for this reason, the objective of this paper is to investigate the economic performance of biomethane plants and their process monitoring by electronic systems. Mathematical modeling is here presented to study the financial feasibility of biomethane plants in function of the size (100 m3/h, 250 m3/h, 500 m3/h, 1000 m3/h), the feedstock used (organic fraction of municipal solid waste and a mixture of 30% maize and 70% manure residues on a weight basic) and the destination for final use (fed into the grid, destined for cogeneration or sold as vehicle fuel). From an economic point of view the plant performance is studied by economic tools as Net Present Value and Discounted Payback Time and the uncertainty analysis is implemented using Monte Carlo method. Moreover, from a technical point of view, process monitoring is analyzed to understand what happens in a biomethane plant and help to maintain a stable process. The results show that the profitability of biomethane plants is verified in several scenarios presenting losses only if subsidies were removed
Electronically Tunable First Order AP/LP and LP/HP Filter Topologies Using Electronically Controllable Second Generation Voltage Conveyor (CVCII)
In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or voltage gains can be electronically varied. Here, in particular, the proposed filter topologies are based on two CVCIIs, one resistor and one capacitor. In the first topology VLP/IAP/VAP and in the second topology ILP/VLP/IHP/VHP outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (Icon) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (f0) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (Vcon). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing Icon from 0.5 µA to 50 µA, f0 is varied from 89 kHz to 1 MHz. Similarly, for a Vcon variation from −0.9 V to 0.185 V, the gains of IAP and IHP vary from 30 dB to 0 dB and those of VAP and VHP vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW
Electronic Interface for Lidar System and Smart Cities Applications
This work deals with the design of a new readoutelectronics for silicon photomultipliers sensors. The so-calledSiPMs sensors are an emerging technology currentlydiffusing in many applications and, among them, in thedefinition of a new generation of LIDAR systems. Thelatter, nowadays have a primary role in the evolutionprocess that is involving Smart Cities, being an enablingtechnology in different fields. The solution here proposed isrealized at electronic level with a 150 nm technology processfrom LFoundry and results provide a feasibledemonstration of the capability of the proposed designapproach to be employed in practical application
Noise analysis and optimization of VCII-based SiPM interface circuit
AbstractRecently, second generation voltage conveyor (VCII)-based transimpedance amplifiers (TIAs) have begun to find their way in different applications, among which, silicon photomultipliers (SiPMs) interfacing circuitry. There are many advantages which make VCII-based TIAs attractive over conventional circuits: the intrinsic low impedance at VCII current input Y port is very helpful to mitigate the effect of high value sensor capacitance and provides fast response time; the achieved bandwidth is high and due to current mode operation; the circuits enjoy the low-voltage low-power features. As signal-to-noise ratio is a crucial parameter in SiPMs interface circuit applications, here we consider the noise specifications and optimization of VCII-based SiPM interface circuits. The noise model of VCII is introduced and equivalent noise of a VCII-based interface circuit is derived. Methods to optimize trade-offs existing between key parameters including power consumption, gain and noise performance are discussed. Simulation results are also provided showing a considerable reduction of two orders of magnitude in most of the noise performances when compared to the previous work while preserving other performance parameters
SAFETY MONITORING BY MEANS OF SENSOR NETWORKS DISTRIBUTED WITHIN THE FOSSA SITE PLAN
Abstract. The seismic event of 6 April 2009 has inevitably left its mark on the history of the entire territory of L'Aquila (Italy), completely devastating the town and much of the province. Within such frantic and extensive reconstruction activity, the resulting construction works could not but draw attention to some issues of fundamental importance such as coordinated planning, safety, respect for the rules and above all the rebirth of the territory. This research is aimed at drawing up the site plan for Fossa, a municipality in the Province of L'Aquila and not far from the region capital of Abruzzo, Italy. The main objective is to create a monitoring standard by means of a dedicated sensors network and detailed strategies in order to coordinate, guide and support the single actions of intervention through design behaviours and highly technological tools. The Plan is configured as a tool for participatory planning, with the active involvement of planners, companies and citizens, whose common goal is the preservation of the identity of locations, the mitigation of seismic risk and the enhancement of the cultural heritage of the Municipality of Fossa. Implementation of this work is the application of technological systems for construction site monitoring: a concrete response to the growing demand for organized management of the construction process on site and safety in the workplace can be achieved through the use of systems and rational control and management procedures that include the use of innovative technologies
A Combined 90/900 MHz IC Architecture for Smart Tag Application
In this work we present a combined 90/900 MHz Energy Harvesting Architecture for active smart tag Application. The harvester takes advantages from a dedicated diplexer and a power manager for battery life enhancement purposes. The system has been optimized in the 900 MHz frequency range by analyzing a probabilistic approach used for modeling the possible amount of Global System for Mobile communication (GSM) energy that could be harvested while a fixed power downlink scenario has been adopted for the 90MHz band. A preliminary IC system with a 0.18μm CMOS SMIC technology has been designed and optimized at 90 and 900 MHz while discrete element board, to be integrated with the proposed IC, with commercial components has been developed and tested. Concerning simulation results on the IC design they have confirmed that the integrated system handles an incoming power typically ranging from -25 dBm to 5 dBm by rectifying the variable input signals into a DC voltage source with an average 50% efficiency
- …