Energy and performance models for clocked and asynchronous communication

Journal ArticleParameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked flopped, clocked time-borrowing latch protocols, asynchronous two-cycle, four-cycle, delay-insensitive, and source synchronous. The paper focuses on communication costs which have the potential to throttle design performance as scaling continues. The models can also be applied to logic. The equations share common parameters to allow apples-to-apples comparisons against different design targets and pipeline methodologies. By applying the parameters to various design targets, one can determine when unclocked communication is superior at the physical level to clocked communication in terms of energy for a given bandwidth. Comparisons between protocols at fixed targets also allow designers to understand tradeoffs between implementations that have a varying degree of timing assumptions and design requirements

Speech Communication

Contains report on one research project.U. S. Air Force (Electronics Systems Division) under Contract AF 19(628)-5661National Institutes of Health (Grant 5 RO1 NB-04332-05)National Institutes of Health (Grant 1 PO1 GM-14940-01)Joint Services Electronics Programs (U. S. Army, U. S. Navy, and U. S. Air Force) under Contract DA 28-043-AMC-02536(E

The Impact of Welfare Reform on Leaver Characteristics, Employment and Recidivism: An Analysis of Maryland and Missouri

State and federal reforms of the 1990s transformed the U.S. cash assistance program for single parents and their children. Despite an extensive literature examining these changes and their impacts, there have been few studies that consider the effects of these reforms from the perspective of the recent period. The analysis here focuses on the characteristics and employment of welfare recipients in Maryland and Missouri, 1991-2004. We find that there has been only modest change in the observable characteristics of those entering, remaining on or leaving welfare, but the importance of employment has grown for each of these groups. We also examine the dynamics of employment and welfare recidivism, comparing cohorts of leavers prior to and after welfare reform. We find that after welfare reform leavers are much more likely to be working. Although in Maryland those working have earnings that are somewhat below employed leavers prior to reform, in Missouri earnings for employed leavers are unchanged. In both states, the types of jobs leavers hold have not changed substantially, and leavers are less likely to return to welfare following reform.welfare reform

Power reduction through physical placement of asynchronous routers

Journal ArticleOur work reduces power consumption by minimizing wirelength and hop-count of an asynchronous NoC using simulated annealing and force-directed algorithms. Asynchronous NoCs (aNoCs) can provide important benefits over clocked NoCs. However, there is little published research on generating a custom, optimized aNoC for a fixedfunction, power-constrained system-on-chip (SoC). Such tools must consider physical SoC properties and especially NoC link delay and power. Our research is motivated by this need, and the mantra that ?transistors are fast, wires are slow and power-hungry,? due to process scaling differences between transistors and global wires

Network simplicity for latency insensitive cores

Journal ArticleIn this paper we examine a latency insensitive net- work composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core. We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design. This concept of a simplified network, along with latency insensitive cores lends itself well to meeting the needs of low-power interconnect components in future design processes

The post office experience: designing a large asynchronous chip

Journal ArticleThe Post Office is an asynchronous, 300,000 transistor, full-custom CMOS chip designed as the communication component for the Mayfly scalable parallel processor. Performance requirements led to the development of a design style which permits the design of sequential circuits operating under a restricted form of multiple input change sign alling called burst-mode. The Post Office complexity forced us to develop a set of design fools capable of correctly synthesizing transistor circuits front state machine and equation specifications, and capable of verifying the correctness of the resultant circuity using implementation specific timing assumptions. The paper provides a case study of this design experience

Symbolic verification of timed asynchronous hardware protocols

pre-printCorrect interaction of asynchronous protocols re- quires verification. Timed asynchronous protocols add another layer of complexity to the verification challenge. A methodology and automated tool flow have been developed for verifying systems of timed asynchronous circuits through compositional model checking of formal models with symbolic methods. The approach uses relative timing constraints to model timing in asynchronous hardware protocols - a novel mapping of timing into the verification flow. Relative timing constraints are enforced at the interface external to the protocol component. SAT based and BDD based methods are explored employing both interleaving and simultaneous compositions. We present our representation of relative timing constraints, its mapping to a formal model, and results obtained using NuSMV on several moderate sized asynchronous protocol examples. The results show that the capability of previous methods is enhanced to enable the hierarchical verification of substantially larger timed systems

Comparing energy and latency of asynchronous and synchronous NoCs for embedded SoCs

Journal ArticlePower consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network on-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires